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ST92141
8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL
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Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation (internal clock) @ 5V10% voltage range -40C to +85C Operating Temperature Range Fully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal (3-5 MHz) Minimum Instruction Cycle time: 160 ns - (@ 25 MHz internal clock frequency) Internal Memory: - EPROM/OTP/FASTROM 16K bytes - RAM 512 bytes 224 general purpose registers available as RAM, accumulators or index pointers (register file) 32-pin Dual Inline and 34-pin Small Outline Packages 15 programmable I/O pins with Schmitt Trigger input, including 4 high sink outputs (20mA @ VOL=3V) 4 Wake-up Interrupts (one usable as NonMaskable Interrupt) for emergency event management 3-phase Induction Motor Controller (IMC) Peripheral with 3 pairs of PWM outputs and asynchronous emergency stop Serial Peripheral Interface (SPI) with Master/ Slave Mode capability 16-bit Timer with 8-bit Prescaler usable as a Watchdog Timer 16-bit Standard Timer with 8-bit Prescaler 16-bit Extended Function Timer with Prescaler, 2 Input Captures and 2 Output Compares 8-bit Analog to Digital Converter allowing up to 6 input channels with autoscan and watchdog capability Low Voltage Detector Reset Rich Instruction Set with 14 Addressing Modes Division-by-Zero trap generation Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third Parties
PSDIP32
SO34 Shrink
CSDIP32W
DEVICE SUMMARY
DEVICE ST92P141 ST92E141 ST92T141 Program Memory (Bytes) 16K FASTROM 16K EPROM 16K OTP RAM (Bytes) 512 512 512 PACKAGE PSDIP32/ SO34 CSDIP32W PSDIP32/ SO34
Rev. 1.7
October 2001 1/179
9
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 3-phase Induction Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 Standard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 Extended Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.11 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 I/O Port Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.1 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.2 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.4 DMASR: DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179. 38 ... 3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.9 NMI/WKP0 LINE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.9.1 NMI/Wake-Up Event Handling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9.2 NMI/Wake-Up Event Handling in STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9.3 Unused Wake Up Management Unit lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 55 3.12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.12.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.12.4 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4 EM CONFIGURATION REGISTERS (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.1 PLL Clock Multiplier Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.2 CPU Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6.1 Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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6.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.1.4 WDT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.4 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.4 Tacho Counter Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.5 IMC Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.6 IMC Output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.4.7 NMI management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.5 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.6 ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 179 7.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
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Table of Contents
9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 174 176 176 178
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST92141 microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt controller, and the Memory Management Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space. Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt bus which connects the interrupt controllers in the on-chip peripherals with the core. Note: The DMA features of the ST9+ core are not used by the on-chip peripherals of the ST92141. This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected by software according to the requirements of the application. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered either by the Phase Locked Loop controlled by the RCCU (Reset and Clock Control Unit), directly by the oscillator or by an external source (dedicated Pin or Alternate Function). Slow Mode. Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and RCCU Clock Divider. Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral with interrupt capability and interrupt controller are kept running at a frequency that can be programmed by software in the RCCU registers. In this mode, the power consumption of the device can be reduced by more than 95% (Low Power WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating. If however the Watchdog is enabled, the HALT instruction has no effect. The main difference between Halt mode and Stop mode is that a reset is necessary to exit from Halt mode which causes the system to be reinitialized. Stop Mode. When Stop mode is requested by executing the STOP sequence (see Wake-up Management Unit section), the CPU and the peripherals stop operating. Operations resume after a wake-up line is activated. The difference between Stop mode and Halt mode is in the way the CPU exits each state: when the STOP sequence is executed, the status of the registers is recorded, and when the system exits from Stop mode the CPU continues execution with the same status, without a system reset. The Watchdog counter, if enabled, is stopped. After exiting Stop mode it restarts counting from where it left off. When the MCU exits from STOP mode, the oscillator, which was also sleeping, requires a start-up time to restart working properly. An internal counter is present to guarantee that, after exiting Stop Mode, all operations take place with the clock stabilised. 1.1.3 System Clock A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 25MHz.
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1.1.4 Low Voltage Reset The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD works both during power-on as well as when the power supply drops (brown-out). The reference value for the voltage drop is lower than the reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). 1.1.5 I/O Ports The I/O lines are grouped into two I/O Ports and can be configured on a bit basis to provide timing, status signals, an address/data bus for timer inputs and outputs, analog inputs, external wake-up lines and serial or parallel I/O. 1.1.6 3-phase Induction Motor Controller The IMC controller is designed for variable speed motor control applications. Three pairs of PWM outputs are available for controlling a three-phase motor drive. Rotor speed feedback is provided by capturing a tachogenerator input signal. Emergency stop is provided by putting the PWM outputs in high impedance mode upon asynchronous faulty event on NMI pin. 1.1.7 Watchdog Timer (WDT) The Watchdog timer can be used to monitor system integrity. When enabled, it generates a reset after a timeout period unless the counter is refreshed by the application software. For additional security, watchdog function can be enabled by hardware using a specific pin.
1.1.8 Standard Timer The standard timer includes a programmable 16bit down-counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.9 Extended Function Timer The Extended Function Timer can be used for a wide range of standard timing tasks. It has a 16-bit free running counter with programmable prescaler. Each timer can have up to 2 input capture and 2 output compare pins with associated registers. This allows applications to measure pulse intervals or generate pulse waveforms. Timer overflow and other events are flagged in a status register with optional interrupt generation. 1.1.10 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, or IC bus communication standards. 1.1.11 Analog/Digital Converter (ADC) The ADC provides up to 6 analog inputs with onchip sample and hold. The analog watchdog generates an interrupt when the input voltage moves out of a preset threshold.
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Figure 1. ST92141 Block Diagram
EPROM/ FASTROM 16K MEMORY BUS RAM 512 bytes Register File 256 bytes 8/16-bit CPU REGISTER BUS Interrupt Management ST9+ CORE
Fully Prog.
I/Os
P3[6:0] P5[7:0]
WATCHDOG
NMI WKUP[3:0] INT0 INT6
WDIN WDOUT
SPI
MISO MOSI SCK SSN
OSCIN OSCOUT RESET INTCLK CK_AF
RCCU + LVD
A/D Converter with analog watchdog
AIN[7:2] EXTRG
ICAP1 OCMP1 ICAP2 OCMP2 EXTCLK STIN STOUT
IMC EF TIMER
TACHO UH UL VH VL WH WL
STIM TIMER
All alternate functions (Italic characters) are mapped on Port3 and Port5
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1.2 PIN DESCRIPTION
VDD MOSI/P3.0 MISO/P3.1 SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 AVDD AVSS INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN5/P5.5 AIN4/P5.4 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2
1
32
16
17
VSS TACHO VH VL WH WL UH UL VPP P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN VSS VDD
ST92E141
PSDIP32/CSDIP32W Package
VDD MOSI/P3.0 MISO/P3.1 SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 N.C. AVDD AVSS INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN5/P5.5 AIN4/P5.4 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2
1
34
17
18
VSS TACHO VH VL WH WL UH UL N.C. VPP P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN VSS VDD SO34 Package
ST92E141
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Table 1. Power Supply Pins
SDIP32 SO34 Name Function Programming voltage for EPROM/OTP devices. Must be connected to VSS in user mode.
Table 2. Primary Function pins
SDIP32 26 30 28 21 Name Function SO34 33 28 32 30 27 31 29 22 20 21
VPP
24
25 18 1 19 34 10 11
TACHO UH VH WH UL VL WL
Signal input from a tachogenerator to the IMC controller for 31 measuring the rotor speed U-phase PWM output signal V-phase PWM output signal W-phase PWM output signal
VDD VSS AVDD AVSS
Main power supply voltage (5V 17 10% (2 pins internally connected) 1 Digital Circuit Ground (2 pins internally connected) Analog VDD of the Analog to Digital Converter 18 32 9
The complemented UH, VH, WH 25 output signals with added dead 29 time to avoid crossover conduc27 tion from the power driver Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the memory location pointed to by the vector contained in memory locations 00h and 01h
Analog VSS of the Analog to Digit10 al Converter
RESET
OSCIN
OSCIN is the input of the oscillator inverter and internal clock generator. OSCIN and OSCOUT connect a parallel-resonant crys- 19 tal (3 to 5 MHz), or an external source to the on-chip clock oscillator and buffer OSCOUT is the output of the os20 cillator inverter
OSCOUT
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1.2.1 I/O Port Configuration All ports can be individually configured as input, bidirectional, output, or alternate function. Refer to the Port Bit Configuration Table in the I/O Port Chapter. All I/Os are implemented with a High Hysteresis or Standard Hysteresis Schmitt trigger function (See Electrical Characteristics). Weak Pull-Up = This column indicates if a weak pull-up is present or not (refer to Table 3). - If WPU = yes, then the WPU can be enabled/disable by software - If WPU = no, then enabling the WPU by software has no effect All port output configurations can be software selected on a bit basis to provide push-pull or open drain driving capabilities. For all ports, when configured as open-drain, the voltage on the pin must never exceed the VDD power line value (refer to Electrical characteristics section). Table 3. I/O Port Characteristics
Input Port 3[4:0] Schmitt trigger (High Hysteresis) Port 3[6:5] Schmitt trigger (High Hysteresis) Port 5.0 Schmitt trigger (High Hysteresis) Port 5.1 Port 5.2 Schmitt trigger (High Hysteresis) Schmitt trigger (Standard Hysteresis)
1.2.2 I/O Port Reset State I/Os are reset asynchronously as soon as the RESET pin is asserted low. All I/Os are forced by the Reset in "floating input" configuration mode. WARNING When a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always inputs to the alternate function module declared as input. When any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. When a given pin is declared to be connected to an analog alternate function input (ADC input for example) and if this pin is programmed in the "AF-OD" mode, the digital input path is disconnected from the pin to prevent any DC consumption.
Output Push-Pull/OD
Weak Pull-Up Reset State Yes Floating input Floating input Floating input Floating input Floating input Floating input
Push-Pull/OD (HC) Yes Push-Pull/OD (HC) Yes Push-Pull/OD Push-Pull/OD Yes Yes Push-Pull/OD (HC) Yes
Port 5[7:3] Schmitt trigger (Standard Hysteresis)
Legend: OD = Open Drain; HC= High current
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Table 4. ST92141 Alternate functions
Port Name P3.0 P3.1 General Purpose I/O Pin No. SDIP32 PSO34 2 3 2 3 MOSI MISO WKUP3 P3.2 4 4 STIN SCK P3.3 5 5 SSN STOUT EXTRG OCPM2 INT6 OCMP1 ICAP1 WKUP2 ICAP2 WKUP1 NMI WKUP0 AIN2 P5.2 16 17 INT0 WDIN AIN3 P5.3 15 16 EXTCLK WDOUT P5.4 P5.5 P5.6 14 13 12 15 14 13 AIN4 AIN5 AIN6 CK_AF AIN7 INTCLK Alternate Functions I/O SPI Master Output/Slave Input Data I/O SPI Master Input/Slave Output Data I I Wake-up line 3 Standard Timer Input
I/O SPI Serial Clock Input/Output I O I O I O I I I I I I I I I I I O I I I I I O SPI Slave Select Standard Timer Output A/D External trigger Ext. Timer Output Compare 2 External Interrupt 6 Ext. Timer - Output Compare 1 Ext. Timer - Input Capture 1 Wake-up line 2 Ext. Timer - Input Capture 2 Wake-up line 1 Not maskable Int. Wake-up line 0 Analog Data Input 2 External Interrupt 0 Watchdog input Analog Data Input 3 Ext. Timer - Input Clock Watchdog Output Analog Data Input 4 Analog Data Input 5 Analog Data Input 6 Clock Alternative Source Analog Data Input 7 Internal Main Clock
P3.4
6
6
P3.5
7
7
P3.6 All ports useable for general purpose I/O (input, output or bidirectional)
8
8
P5.0
23
24
P5.1
22
23
P5.7
11
12
How to configure the I/O ports To configure the I/O ports, use the information in Table 3 and Table 4 and the Port Bit Configuration Table in the I/O Ports Chapter on page 81. I/O note = The hardware characteristics fixed for each port line in Table 3. All I/O inputs have Schmitt trigger fixed by hardware so selecting CMOS or TTL input by software
has no effect, the input will always be Schmitt Trigger. In particular, the Schmitt Triggers present on the P5[7:2] pins have a standard hysteresis whereas the remaining pins have Schmitt Triggers with High Hysteresis (refer to Electrical Specifications). Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time:
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An alternate function can be selected as follows. AF Inputs: - AF is selected implicitly by enabling the corresponding peripheral. Exceptions to this are ADC analog inputs which must be explicitly selected as AF by software. AF Outputs or Bidirectional Lines: - In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: Standard Timer input AF: STIN, Port: P3.2, I/O Note: Schmitt trigger. Write the port configuration bits: P3C2.2=1 P3C1.2=0 P3C0.2=1 or P3C2.2=0 P3C1.2=0 P3C0.2=1
Enable the Standard Timer input by software as described in the STIM chapter. Example 2: Standard Timer output AF: STOUT, Port: P3.3 Write the port configuration bits (for AF output push-pull): P3C2.3=0 P3C1.3=1 P3C0.3=1 Example 3: ADC analog input AF: AIN2, Port: P5.2, I/O Note: does not apply to analog inputs Write the port configuration bits: P5C2.2=1 P5C1.2=1 P5C0.2=1
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1.3 MEMORY MAP 1.3.1 Memory Configuration The Program memory space of the ST92141, 16K bytes of directly addressable on-chip memory, is fully available to the user. The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predetermined function except segment 21h which is reserved for use by STMicroelectronics. 1.3.2 EPROM Programming The 16K bytes of EPROM memory of the ST92E141 may be programmed by using the EPROM Programming Boards (EPB) or gang programmers available from STMicroelectronics. EPROM Erasing The EPROM of the windowed package of the ST92E141 may be erased by exposure to Ultra-Violet light. The erasure characteristic of the ST92E141 is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000A. It should be noted that sunlight Figure 2. Memory Map
220000h 21FFFFh
and some types of fluorescent lamps have wavelengths in the range 3000-4000A. It is thus recommended that the window of the ST92E141 packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 30 minutes using an ultraviolet lamp with 12000mW/cm2 power rating. The ST92E141 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. Table 5. First 6 Bytes of Program Space
0 1 2 3 4 5 Address Address Address Address Address Address high of Power on Reset routine low of Power on Reset routine high of Divide by zero trap Subroutine low of Divide by zero trap Subroutine high of Top Level Interrupt routine low of Top Level Interrupt routine
SEGMENT 21h 64 Kbytes
Reserved
210000h 20FFFFh
Reserved
20C000h 20BFFFh 200200h
PAGE 83 - 16 Kbytes PAGE 82 - 16 Kbytes
208000h 207FFFh
SEGMENT 20h 64 Kbytes
Reserved Reserved
Internal RAM 512 bytes
PAGE 81 - 16 Kbytes
204000h 203FFFh
PAGE 80 - 16 Kbytes
200000h 200000h 00FFFFh
PAGE 3 - 16 Kbytes
00C000h 00BFFFh
SEGMENT 0 64 Kbytes FASTROM/EPROM 16 Kbytes
004000h 003FFFh 000000h
Internal ROM max. 64 Kbytes
PAGE 2 - 16 Kbytes
008000h 007FFFh
PAGE 1 - 16 Kbytes
004000h 003FFFh
PAGE 0 - 16 Kbytes
000000h
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1.4 REGISTER MAP The following pages contain a list of ST92141 registers, grouped by peripheral or function. Be very careful to correctly program both: - The set of registers dedicated to a particular function or peripheral. - Registers common to other functions. - In particular, double-check that any registers with "undefined" reset values have been correctly initialised. WARNING: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entries in the Interrupt Vector table do not overlap.
Table 6. Common Registers
Function or Peripheral ADC WDT I/O PORTS EXTERNAL INTERRUPT RCCU Common Registers CICR + NICR + I/O PORT REGISTERS CICR + NICR + EXTERNAL INTERRUPT REGISTERS + I/O PORT REGISTERS I/O PORT REGISTERS + MODER INTERRUPT REGISTERS + I/O PORT REGISTERS INTERRUPT REGISTERS + MODER
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Table 7. Group F Pages Resources available on the ST92141 devices:
Register 0 R255 R254 R253 R252 R251 R250 WDT R249 MMU R248 EFT0 R247 R246 Res. R245 R244 R243 R242 Res. R241 Res. R240 RCCU SPI0 STIM0 Res. MMU RCCU EXT INT PORT 5 Res. Res. Res. Res. RCCU IMC A/D0 Res. Res. WCR IMC Res. Res. Res. PORT 3 2 Res. 3 7 11 21 Page 28 48 51 55 57 63
Res. WU
EM
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Table 8. Detailed Register Map
Page (Decimal) Block Reg. No. R230 R231 R232 R233 Core R234 R235 R236 N/A R237 R238 R239 R224 I/O Port 5:4,2:0 R225 R226 R228 R229 R242 R243 INT R244 R245 R246 0 R247 R248 R249 WDT R250 R251 R252 I/O 2 Port 3 I/O 3 Port 5 R252 R253 R254 R244 R245 R246 R240 7 SPI R241 R242 R243 R240 11 STIM R241 R242 R243 Register Name CICR FLAGR RP0 RP1 PPR MODER USPHR USPLR SSPHR SSPLR P0DR P1DR P2DR P4DR P5DR EITR EIPR EIMR EIPLR EIVR NICR WDTHR WDTLR WDTPR WDTCR WCR P3C0 P3C1 P3C2 P5C0 P5C1 P5C2 SPDR SPCR SPSR SPPR STH STL STP STC Description Central Interrupt Control Register Flag Register Pointer 0 Register Pointer 1 Register Page Pointer Register Mode Register User Stack Pointer High Register User Stack Pointer Low Register System Stack Pointer High Reg. System Stack Pointer Low Reg. Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 4 Data Register Port 5 Data Register External Interrupt Trigger Register External Interrupt Pending Reg. External Interrupt Mask-bit Reg. External Interrupt Priority Level Reg. External Interrupt Vector Register Nested Interrupt Control Watchdog Timer High Register Watchdog Timer Low Register Watchdog Timer Prescaler Reg. Watchdog Timer Control Register Wait Control Register Port 3 Configuration Register 0 Port 3 Configuration Register 1 Port 3 Configuration Register 2 Port 5 Configuration Register 0 Port 5 Configuration Register 1 Port 5 Configuration Register 2 SPI Data Register SPI Control Register SPI Status Register SPI Prescaler Register Counter High Byte Register Counter Low Byte Register Standard Timer Prescaler Register Standard Timer Control Register Reset Value Hex. 87 00 xx xx xx E0 xx xx xx xx FF FF FF FF FF 00 00 00 FF x6 00 FF FF FF 12 7F 00 00 00 FF 00 00 00 00 00 00 FF FF FF 14 145 145 146 146 95 95 95 95 79 52 53 53 53 54 54 90 90 90 90 91 79 Doc. Page 52 24 26 26 28 28 30 30 30 30
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Page (Decimal)
Block
Reg. No. R240 R241 R242
Register Name DPR0 DPR1 DPR2 DPR3 CSR ISR DMASR EMR1 EMR2 IC1HR IC1LR IC2HR IC2LR CHR CLR ACHR ACLR OC1HR OC1LR OC2HR OC2LR CR1 CR2 SR CR3 PCR0 PCR1 PCR2 PSR OPR IMR DTG IMCIVR
Description Data Page Register 0 Data Page Register 1 Data Page Register 2 Data Page Register 3 Code Segment Register Interrupt Segment Register DMA Segment Register EM Register 1 EM Register 2 Input Capture 1 High Register Input Capture 1 Low Register Input Capture 2 High Register Input Capture 2 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Output Compare 1 High Register Output Compare 1 Low Register Output Compare 2 High Register Output Compare 2 Low Register Control Register 1 Control Register 2 Status Register Control Register 3 Peripheral Control Register 0 Peripheral Control Register 1 Peripheral Control Register 2 Polarity Selection Register Output Peripheral Register Interrupt Mask Register Dead Time Generator Register IMC Interrupt Vector Register
Reset Value Hex. xx xx xx xx 00 xx xx 80 0F xx xx xx xx FF FC FF FC 80 00 80 00 00 00 00 00 80 00 00 00 00 00 00 xx
Doc. Page 35 35 35 35 36 36 36 62 62 108 108 108 108 109 109 109 109 110 110 110 110 111 112 113 113 130 130 131 131 132 132 133 133
MMU 21
R243 R244 R248 R249 R245 R246 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R248 R249 R250 R251 R252 R253 R254 R255
EM
28
EFT
48
IMC
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Page (Decimal)
Block
Reg. No. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R240
Register Name TCPTH TCPTL TCMP ISR TPRSH TPRSL CPRS REP CPWH CPWL CPVH CPVL CPUH CPUL CP0H CP0L CLKCTL CLK_FLAG PLLCONF WUCTRL WUMRH WUMRL WUTRH WUTRL WUPRH WUPRL D0R D1R D2R D3R D4R D5R D6R D7R LT6R LT7R UT6R UT7R CRR CLR ICR IVR
Description Tacho Capture Register High Tacho Capture Register Low Tacho Compare Register Interrupt Status Register Tacho Prescaler Register High Tacho Prescaler Register Low PWM Counter Prescaler Register Repetition Counter Register Compare Phase W Preload Register High Compare Phase W Preload Register Low Compare Phase V Preload Register High Compare Phase V Preload Register Low Compare Phase U Preload Register High Compare Phase U Preload Register Low Compare 0 Preload Register High Compare 0 Preload Register Low Clock Control Register Clock Flag Register PLL Configuration Register Wake-Up Control Register Wake-Up Mask Register High Wake-Up Mask Register Low Wake-Up Trigger Register High Wake-Up Trigger Register Low Wake-Up Pending Register High Wake-Up Pending Register Low Channel 0 Data Register Channel 1 Data Register Channel 2 Data Register Channel 3 Data Register Channel 4 Data Register Channel 5 Data Register Channel 6 Data Register Channel 7 Data Register Channel 6 Lower Threshold Reg. Channel 7 Lower Threshold Reg. Channel 6 Upper Threshold Reg. Channel 7 Upper Threshold Reg. Compare Result Register Control Logic Register Interrupt Control Register Interrupt Vector Register
Reset Value Hex. xx xx xx 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 48, 28 xx 00 00 00 00 00 00 00 xx xx xx xx xx xx xx xx xx xx xx xx 0F 00 0F x2
Doc. Page 125 125 125 36 127 127 127 127 128 128 128 128 129 129 129 129 69 70 71 59 60 60 61 61 61 61 151 151 151 151 151 151 151 151 152 152 152 152 153 154 155 155
51
IMC
55
RCCU
R242 R246 R249 R250 R251
57
WUIMU
R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255
63
ADC
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details.
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2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available. Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the Core. This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources. which hold data and control bits for the on-chip peripherals and I/Os. - A single linear memory space accommodating both program and data. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in this common address space. The total addressable memory space of 4 Mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further subdivided into four pages of 16 Kbytes, as illustrated in Figure 3. A Memory Management Unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File The Register File consists of (see Figure 4): 2.2 MEMORY SPACES - 224 general purpose registers (Group 0 to D, There are two separate memory spaces: registers R0 to R223) - The Register File, which comprises 240 8-bit - 6 system registers in the System Group (Group registers, arranged as 15 groups (Group 0 to E), E, registers R224 to R239) each containing sixteen 8-bit registers plus up to - Up to 64 pages, depending on device configura64 pages of 16 registers mapped in Group F, tion, each containing up to 16 registers, mapped to Group F (R240 to R255), see Figure 5. Figure 3. Single Program and Data Memory Address Space
Address
3FFFFFh 3F0000h 3EFFFFh 3E0000h
Data 16K Pages
255 254 253 252 251 250 249 248 247
Code 64K Segments
63
62
up to 4 Mbytes
135 134 133 132
21FFFFh 210000h 20FFFFh
Reserved
33
02FFFFh 020000h 01FFFFh 010000h 00FFFFh 000000h
11 10 9 8 7 6 5 4 3 2 1 0
2
1
0
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MEMORY SPACES (Cont'd) Figure 4. Register Groups
UP TO 64 PAGES
Figure 5. Page Pointer for Group F mapping
PAGE 63
255 240 F PAGED REGISTERS 239 E SYSTEM REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
PAGE 5 R255 PAGE 0
R240 R234 224 GENERAL PURPOSE REGISTERS R224 PAGE POINTER
VA00432
R0
VA00433
Figure 6. Addressing the Register File
REGISTER FILE 255 240 F PAGED REGISTERS 239 E SYSTEM REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
VR000118
GROUP D R195 (R0C3h) R207
(1100) (0011) GROUP C
R195 R192 GROUP B
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MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 6). Group D registers can only be addressed in Working Register mode. Note that an upper case "R" is used to denote this direct addressing mode. Working Registers Certain types of instruction require that registers be specified in the form "rx", where x is in the range 0 to 15: these are known as Working Registers. Note that a lower case "r" is used to denote this indirect addressing mode. Two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 2.3.3 Register Pointing Techniques, and illustrated in Figure 7 and in Figure 8. System Registers The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. These registers are described in greater detail in Section 2.3 SYSTEM REGISTERS. Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These are addressed using any register addressing mode, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.
Therefore if the Page Pointer, R234, is set to 5, the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers therefore depends on the peripherals which are present in the specific ST9 family device. In other words, pages only exist if the relevant peripheral is present. Table 9. Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group F Group E Group D Group C Group B Group A Group 9 Group 8 Group 7 Group 6 Group 5 Group 4 Group 3 Group 2 Group 1 Group 0
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2.3 SYSTEM REGISTERS The System registers are listed in Table 10 System Registers (Group E). They are used to perform all the important system settings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers. Table 10. System Registers (Group E)
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SSPLR SSPHR USPLR USPHR MODE REGISTER PAGE POINTER REGISTER REGISTER POINTER 1 REGISTER POINTER 0 FLAG REGISTER CENTRAL INT. CNTL REG PORT5 DATA REG. PORT4 DATA REG. PORT3 DATA REG. PORT2 DATA REG. PORT1 DATA REG. PORT0 DATA REG.
Note: If an MFT is not included in the ST9 device, then this bit has no effect. Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending Bit 5 = TLI: Top Level Interrupt bit. 0: Top Level Interrupt is acknowledged depending on the TLNM bit in the NICR Register. 1: Top Level Interrupt is acknowledged depending on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter). Bit 4 = IEN: Interrupt Enable . This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. 1: Enable Interrupts Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode. Bits 2:0 = CPL[2:0]: Current Priority Level. These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the current interrupt is replaced by one of a higher priority, the current priority value is automatically stored until required in the NICR register.
2.3.1 Central Interrupt Control Register Please refer to the "INTERRUPT" chapter for a detailed description of the ST9 interrupt philosophy. CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h)
7 GCEN TLIP TLI IEN IAM 0 CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set after the Reset cycle.
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SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the system stack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h)
7 C Z S V DA H 0 DP
decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator become zero, following one of the above operations. Bit 5 = S: Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 = V: Overflow Flag. The Overflow flag is affected by the same instructions as the Zero and Sign flags. When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two's-complement notation. Bit 3 = DA: Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condition by the programmer. Bit 2 = H: Half Carry Flag. The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 = DP: Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details.
Bit 7 = C: Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Complement Carry Flag (ccf) instruction. Bit 6 = Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont'd) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note: In the current ST9 devices, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 Register Pointing Techniques Two registers within the System register group, are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register mode. The Set Register Pointer instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and
specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16register mode. The block number should always be an even number in single 16-register mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3 will be interpreted as srp #2 and will allow using R16 ..R31 as r0 .. r15. In single 16-register mode, the working registers are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form "Rxxx".
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SYSTEM REGISTERS (Cont'd) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
This register is only used in the twin register pointing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
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SYSTEM REGISTERS (Cont'd) Figure 7. Pointing to a single group of 16 registers
REGISTER GROUP REGISTER FILE
Figure 8. Pointing to two groups of 8 registers
REGISTER GROUP REGISTER FILE 31
BLOCK NUMBER
BLOCK NUMBER
31 F 30 29 E 28 points to: 27 D 26 25 25 addressed by BLOCK 7 9 9 4 8 7 7 3 6 5 5 2 4 r15 3 1 2 r0 1 0 0 addressed by BLOCK 2 1 GROUP 1 2 3 4 6 8 26 27 REGISTER POINTER 0 set by: 30 29
F
REGISTER POINTER 0 & REGISTER POINTER 1 set by:
srp #2
instruction
E 28
srp0 #2
& D
srp1 #7
instructions point to:
4 r15 GROUP 3 3 r8
2
1
r7 r0 GROUP 1 addressed by BLOCK 2
0 0
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SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present. The paged registers are addressed using the normal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the interrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh)
7 PP5 PP4 PP3 PP2 PP1 PP0 0 0 0
- Management of the clock frequency, - Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h)
7
SSP USP DIV2 PRS2 PRS1
0
PRS0 BRQEN HIMP
Bit 7 = SSP: System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 = USP: User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (reset state). Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2. This bit controls the divide-by-2 circuit operating on the crystal oscillator clock (CLOCK1). 0: Clock divided by 1 1: Clock divided by 2 Bits 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not available. Bit 0 = HIMP: High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance
Bits 7:2 = PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is required. Bits 1:0: Reserved. Forced by hardware to 0. 2.3.5 Mode Register The Mode Register allows control of the following operating parameters: - Selection of internal or external System and User Stack areas,
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SYSTEM REGISTERS (Cont'd) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines. 2.3.6 Stack Pointers Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the "bottom" of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is "pushed" in and post-incremented when data is "popped" out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix "u". To use a stack instruction for a word, the suffix "w" is added. These suffixes may be combined. When bytes (or words) are "popped" out from a stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when data is "popped" from a stack area, the stack contents remain unchanged. Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value. System Stack The System Stack is used for the temporary storage of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: - Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENCSR bit in the EMR2 register is set, then the
Code Segment Register is also pushed onto the System Stack. - Subroutine Calls When a call instruction is executed, only the PC is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. - Link Instruction The link or linku instructions create a C language stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as reserved and must not be used as a general purpose register. The stack pointer registers are located in the System Group of the Register File, this is illustrated in Table 10 System Registers (Group E). Stack Location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as a stacking area. Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group.
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SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined
7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 0 USP8
SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 0 SSP8
USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) Reset value: undefined
7 USP7 USP6 USP5 USP4 USP3 USP2 USP1 0 USP0
SYSTEM STACK POINTER LOW REGISTER (SSPLR) R239 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 0 SSP0
Figure 9. Internal Stack Mode
Figure 10. External Stack Mode
REGISTER FILE STACK POINTER (LOW) F points to: F
REGISTER FILE
STACK POINTER (LOW) & STACK POINTER (HIGH) point to: MEMORY
E STACK D
E
D
STACK 4 4
3
3
2
2
1
1
0
0
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2.4 MEMORY ORGANIZATION Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map.
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2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be Figure 11. Page 21 Registers sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).
Page 21 FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 DMASR ISR R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 MMU EM MMU MMU SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0
Relocation of P[3:0] and DPR[3:0] Registers
DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 1 DPR0
DMASR ISR EMR2 EMR1 CSR P3DR P2DR P1DR P0DR
Bit DPRREM=0 (default setting)
Bit DPRREM=1
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2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space, it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode is implicitly used to address Data memory space if no DMA is being performed. The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains 256 pages of 16 Kbytes. Data paging is performed by extending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted as the identification number of the DPR register to be used. Therefore, the DPR registers Figure 12. Addressing via DPR[3:0] are involved in the following virtual address ranges: DPR0: from 0000h to 3FFFh; DPR1: from 4000h to 7FFFh; DPR2: from 8000h to BFFFh; DPR3: from C000h to FFFFh. The contents of the selected DPR register specify one of the 256 possible data memory pages. This 8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical 22-bit address (see Figure 12). A DPR register cannot be modified via an addressing mode that uses the same DPR register. For instance, the instruction "POPW DPR0" is legal only if the stack is kept either in the register file or in a memory location above 8000h, where DPR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the instruction, unpredictable behaviour could result.
MMU registers DPR0 DPR1 DPR2 DPR3
16-bit virtual address
00
01
10
11
2M
SB
8 bits
14 LSB
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program memory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 13). 2.7 MMU REGISTERS The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register.
Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation If these registers are to be used frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR's locations: R240-243 page 21. Data Page Register relocation is illustrated in Figure 11.
Figure 13. Addressing via CSR, ISR, and DMASR
MMU registers CSR DMASR ISR
16-bit virtual address
1 1 2 Fetching program instruction Data Memory accessed in DMA Fetching interrupt instruction or DMA access to Program Memory
2
3
6 bits
3
22-bit physical address
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MMU REGISTERS (Cont'd) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set.
7 0
DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set.
7 0
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set.
7 0
Bits 7:0 = DPR2_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set.
7 0
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh.
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MMU REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets instruction. CODE SEGMENT REGISTER (CSR) R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h)
7 0 0 CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 0 CSR_0
ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16). The ISR is used to extend the address space in two cases: - Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the interrupt vector table and the interrupt service routine code. See also the Interrupts chapter. - During DMA transactions between the peripheral and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction. 2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined
7 DMA SR_5 DMA SR_4 DMA SR_3 DMA SR_2 DMA SR_1 0 DMA SR_0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16). 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined
7 0 0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
0
0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the address.
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MMU REGISTERS (Cont'd) Figure 14. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
16K
294000h
DPR3 DPR2 DPR1 DPR0 16K 16K 20C000h 200000h 1FFFFFh 240000h 23FFFFh
64K DMASR
040000h 03FFFFh 030000h 020000h
ISR CSR
64K 16K 64K
010000h 00C000h 000000h
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2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if ENCSR is reset. Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR[3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 03. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 Interrupts The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21). If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion. 2.8.3 DMA Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).
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3 INTERRUPTS
3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate Interrupt Service Routine (refer to Figure 15). The ST9 CPU can receive requests from the following sources: - On-chip peripherals - External pins - Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an event occurrence can generate an Interrupt request which depends on the selected mode. Up to eight external interrupt channels, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory. Figure 15. Interrupt Response
n
3.2 INTERRUPT VECTORING The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer). Each peripheral has a specific IVR mapped within its Register File pages. The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thus allowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU. The user Power on Reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR). With one Interrupt Vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. Note: The first 256 locations of the memory segment pointed to by ISR can contain program code. 3.2.1 Divide by Zero trap The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required. Warning. Although the Divide by Zero Trap operates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET).
NORMAL PROGRAM FLOW
INTERRUPT SERVICE ROUTINE
INTERRUPT
CLEAR PENDING BIT
IRET INSTRUCTION
VR001833
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3.2.2 Segment Paging During Interrupt Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compatibility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. ST9+ mode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different.
ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped PC, FLAGR, PC, FLAGR Registers CSR Max. Code Size 64KB No limit for interrupt Within 1 segment Across segments service routine
3.3 INTERRUPT PRIORITY LEVELS The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: - The on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority). - The 9th level (Top Level Priority) is reserved for the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM). 3.4 PRIORITY LEVEL ARBITRATION The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware according to the selected Arbitration Mode. During every instruction, an arbitration phase takes place, during which, for every channel capable of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA). If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR register (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority. 3.4.1 Priority level 7 (Lowest) Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL value. This can be of use in a fully polled interrupt environment. 3.4.2 Maximum depth of nesting No more than 8 routines can be nested. If an interrupt routine at level N is being serviced, no other Interrupts located at level N can interrupt it. This guarantees a maximum number of 8 nested levels including the Top Level Interrupt request. 3.4.3 Simultaneous Interrupts If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel
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PRIORITY LEVEL ARBITRATION (Cont'd) with the highest position in the chain, as shown in Table 11. Table 11. Daisy Chain Priority
Highest Position INTA0 / Watchdog Timer INTA1 / Standard Timer INTB0 / Extended Function Timer INTC1 / SPI INTD0 / RCCU INTD1 / WKUP MGT Induction Motor Controller AD Converter
Lowest Position
3.4.4 Dynamic Priority Level Modification The main program and routines can be specifically prioritized. Since the CPL is represented by 3 bits in a read/write register, it is possible to modify dynamically the current priority value during program execution. This means that a critical section can have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by modifying the CPL during its execution. See Figure 16 Figure 16. Example of Dynamic priority level modification in Nested Mode
INTERRUPT 6 HAS PRIORITY LEVEL 6 Priority Level CPL is set to 7 4 by MAIN program ei INT6 MAIN CPL is set to 5 CPL6 > CPL5: 6 INT6 pending 7 5
INT 6 CPL=6 MAIN CPL=7
3.5 ARBITRATION MODES The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested mode. Concurrent mode is the standard interrupt arbitration mode. Nested mode improves the effective interrupt response time when service routine nesting is required, depending on the request priority levels.
The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested Arbitration Mode. 3.5.1 Concurrent Mode This mode is selected when the IAM bit is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode. Start of Interrupt Routine The interrupt cycle performs the following steps: - All maskable interrupt requests are disabled by clearing CICR.IEN. - The PC low byte is pushed onto system stack. - The PC high byte is pushed onto system stack. - If ENCSR is set, CSR is pushed onto system stack. - The Flag register is pushed onto system stack. - The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. - If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction. End of Interrupt Routine The Interrupt Service Routine must be ended with the iret instruction. The iret instruction executes the following operations: - The Flag register is popped from system stack. - If ENCSR is set, CSR is popped from system stack. - The PC high byte is popped from system stack. - The PC low byte is popped from system stack. - All unmasked Interrupts are enabled by setting the CICR.IEN bit. - If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumes at the interrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). Note: In Concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine's priority. This may cause undesirable interrupt response sequences.
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ARBITRATION MODES (Cont'd) Examples In the following two examples, three interrupt requests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service routine.
Example 1 In the first example, (simplest case, Figure 17) the ei instruction is not used within the interrupt service routines. This means that no new interrupt can be serviced in the middle of the current one. The interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes.
Figure 17. Simple Example of a Sequence of Interrupt Requests with: - Concurrent mode selected and - IEN unchanged by the interrupt routines
0 Priority Level of Interrupt Request
INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7 INT 3 CPL = 7 INT 2 INT 3 INT 4 INT 5 ei CPL = 7 INT 4 CPL = 7
3
4
5
6 INT 5 7 MAIN CPL is set to 7 MAIN CPL = 7
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ARBITRATION MODES (Cont'd) Example 2 In the second example, (more complex, Figure 18), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than the one being serviced. The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-
ice routines being executed in the opposite order of their priority. It is therefore recommended to avoid inserting the ei instruction in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode. WARNING: If, in Concurrent Mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either ENCSR is set or CSR=ISR, otherwise the iret of the innermost interrupt will make the CPU use CSR instead of ISR before the outermost interrupt service routine is terminated, thus making the outermost routine fail.
Figure 18. Complex Example of a Sequence of Interrupt Requests with: - Concurrent mode selected - IEN set to 1 during interrupt service routine execution
0 Priority Level of Interrupt Request
INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7
INT 2 CPL = 7 INT 3 CPL = 7 ei INT 4 CPL = 7 INT 5 CPL = 7 INT 3 CPL = 7
3 INT 2 INT 3 INT 4 INT 5 ei 6 INT 5 7 MAIN CPL is set to 7 CPL = 7 ei
ei
4
5
ei
MAIN CPL = 7
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ARBITRATION MODES (Cont'd) 3.5.2 Nested Mode The difference between Nested mode and Concurrent mode, lies in the modification of the Current Priority Level (CPL) during interrupt processing. The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in the Nested Interrupt Control Register (NICR) by setting the NICR bit corresponding to the CPL value (i.e. if the CPL is 3, the bit 3 will be set). The CPL is then loaded with the priority of the request just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being executed. Start of Interrupt Routine The interrupt cycle performs the following steps:
- All maskable interrupt requests are disabled by clearing CICR.IEN. - CPL is saved in the special NICR stack to hold the priority level of the suspended routine. - Priority level of the acknowledged routine is stored in CPL, so that the next request priority will be compared with the one of the routine currently being serviced. - The PC low byte is pushed onto system stack. - The PC high byte is pushed onto system stack. - If ENCSR is set, CSR is pushed onto system stack. - The Flag register is pushed onto system stack. - The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. - If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction.
Figure 19. Simple Example of a Sequence of Interrupt Requests with: - Nested mode - IEN unchanged by the interrupt routines
Priority Level of Interrupt Request 0 INT 0 CPL=0 CPL6 > CPL3: INT6 pending
INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6
1 INT0 2 INT 2 CPL=2
INT6 INT 3 CPL=3
INT 2 CPL=2
3 INT2 INT3 INT4 INT 5 CPL=5
INT2 INT 4 CPL=4
4
5 ei 6 INT5 7
CPL2 < CPL4: Serviced next
INT 6 CPL=6 MAIN CPL=7
MAIN CPL is set to 7
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ARBITRATION MODES (Cont'd) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: - The Flag register is popped from system stack. - If ENCSR is set, CSR is popped from system stack. - The PC high byte is popped from system stack. - The PC low byte is popped from system stack. - All unmasked Interrupts are enabled by setting the CICR.IEN bit. - The priority level of the interrupted routine is popped from the special register (NICR) and copied into CPL.
- If ENCSR is reset, CSR is used instead of ISR, unless the program returns to another nested routine. The suspended routine thus resumes at the interrupted instruction. Figure 19 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. Figure 20 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routines using the ei instruction) according to their priority level.
Figure 20. Complex Example of a Sequence of Interrupt Requests with: - Nested mode - IEN set to 1 during the interrupt routine execution
Priority Level of Interrupt Request 0
INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2
INT 0 CPL=0 CPL6 > CPL3: INT6 pending INT 2 CPL=2 INT 2 CPL=2
INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6
1 INT0 2 INT 2 CPL=2 ei INT2 INT3 INT4 INT 5 CPL=5 ei ei INT5 7 MAIN CPL is set to 7
INT6 INT 3 CPL=3 INT2
3
4
ei CPL2 < CPL4: Serviced just after ei INT 4 CPL=4 ei INT 4 CPL=4 INT 5 CPL=5 INT 6 CPL=6 MAIN CPL=7
5
6
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3.6 EXTERNAL INTERRUPTS The standard ST9 core contains 8 external interrupts sources grouped into four pairs. Table 12. External Interrupt Channel Grouping
External Interrupt none INT6 none none none none none INT0 Channel INTD1 INTD0 INTC1 INTC0 INTB1 INTB0
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Figure 21. Priority Level Examples
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
1
SOURCE PRIORITY
0
0
0
1
0
0
1
EIPLR
SOURCE PRIORITY
INT.D0: 100=4 INT.D1: 101=5 INT.C0: 000=0 INT.C1: 001=1
INT.A0: 010=2 INT.A1: 011=3 INT.B0: 100=4 INT.B1: 101=5 VR000151
INTA1 INTA0
Each source has a trigger control bit TEA0,..TED1 (R242,EITR.0,..,7 Page 0) to select triggering on the rising or falling edge of the external pin. If the Trigger control bit is set to "1", the corresponding pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the input pin. Each source can be individually masked through the corresponding control bit IMA0,..,IMD1 (EIMR.7,..,0). See Figure 22. The priority level of the external interrupt sources can be programmed among the eight priority levels with the control register EIPLR (R245). The priority level of each pair is software defined using the bits PRL2, PRL1. For each pair, the even channel (A0,B0,C0,D0) of the group has the even priority level and the odd channel (A1,B1,C1,D1) has the odd (lower) priority level.
Figure 21 shows an example of priority levels. Figure 22 gives an overview of the External interrupt control bits and vectors. - The source of the interrupt channel A0 can be selected between the external pin INT0 (when IA0S = "1", the reset value) or the On-chip Timer/ Watchdog peripheral (when IA0S = "0"). - The source of the interrupt channel D0 can be selected between the external pin INT6 (when INT_SEL = "0") or the on-chip RCCU. WARNING: When using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. Table 13. Multiplexed Interrupt Sources
Channel INTA0 INTD0 Internal Interrupt Source Timer/Watchdog RCCU External Interrupt Source INT0 INT6
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EXTERNAL INTERRUPTS (Cont'd) Figure 22. External Interrupts Control Bits and Vectors
n
TEA0
Watchdog/Timer IA0S End of count "0" V7 V6 V5 V4 0 0 VECTOR Priority level PL2A PL1A 0 00 INT A0 request
INT 0 pin
"1"
INTS STIM Interrupt "0" not connected "1"
*
Mask bit IMA0
Pending bit IPA0
V7 V6 V5 V4 0 0 VECTOR Priority level PL2A PL1A 1 Mask bit IMA1
10 INT A1 request
Pending bit IPA1
EFTIS EFT Interrupt "1" not connected "0" V7 V6 V5 V4 0 1 VECTOR Priority level PL2B PL1B 0 Mask bit IMB0 00 INT B0 request
Pending bit IPB0
not connected
V7 V6 V5 V4 0 1 VECTOR Priority level PL2B PL1B 1 Mask bit IMB1
10 INT B1 request
Pending bit IPB1
not connected SPIS SPI Interrupt "1" not connected "0"
V7 V6 V5 V4 1 0 VECTOR Priority level PL2C PL1C 0 Mask bit IMC0
00 INT C0 request
Pending bit IPC0
V7 V6 V5 V4 1 0 VECTOR Priority level PL2C PL1C 1 Mask bit IMC1
10 INT C1 request
Pending bit IPC1
TED0
RCCU interrupt INT_SEL "1" V7 V6 V5 V4 1 1 VECTOR PL2D PL1D 0 Priority level 00 INT D0 request
INT 6 pin
"0" ID1S WUIMU interrupt "1" not connected * "0"
*
Mask bit IMD0
Pending bit IPD0
V7 V6 V5 V4 1 1 VECTOR Priority level PL2D PL1D 1 Mask bit IMD1
10 INT D1 request
Pending bit IPD1
Shared channels, see warning
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3.7 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high (the reset condition) the source is the external pin NMI. If it is low, the source is the Timer/ Watchdog End Of Count. When the source is the NMI external pin, the control bit EIVR.TLTEV (R246.3; Page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. When the selected event occurs, the CICR.TLIP bit (R230.6) is set. Depending on the mask situation, a Top Level Interrupt request may be generated. Two kinds of masks are available, a Maskable mask and a Non-Maskable mask. The first mask is the CICR.TLI bit (R230.5): it can be set or cleared to enable or disable respectively the Top Level Interrupt request. If it is enabled, the global Enable Interrupt bit, CICR.IEN (R230.4) must also be enabled in order to allow a Top Level Request. The second mask NICR.TLNM (R247.7) is a setonly mask. Once set, it enables the Top Level Interrupt request independently of the value of CICR.IEN and it cannot be cleared by the program. Only the processor RESET cycle can clear this bit. This does not prevent the user from ignoring some sources due to a change in TLIS. The Top Level Interrupt Service Routine cannot be interrupted by any other interrupt or DMA request, in any arbitration mode, not even by a subsequent Top Level Interrupt request. Figure 23. Top Level Interrupt Structure
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WARNING. The interrupt machine cycle of the Top Level Interrupt does not clear the CICR.IEN bit, and the corresponding iret does not set it. Furthermore the TLI never modifies the CPL bits and the NICR register. 3.8 ON-CHIP PERIPHERAL INTERRUPTS The general structure of the peripheral interrupt unit is described here, however each on-chip peripheral has its own specific interrupt unit containing one or more interrupt channels, or DMA channels. Please refer to the specific peripheral chapter for the description of its interrupt features and control registers. The on-chip peripheral interrupt channels provide the following control bits: - Interrupt Pending bit (IP). Set by hardware when the Trigger Event occurs. Can be set/ cleared by software to generate/cancel pending interrupts and give the status for Interrupt polling. - Interrupt Mask bit (IM). If IM = "0", no interrupt request is generated. If IM ="1" an interrupt request is generated whenever IP = "1" and CICR.IEN = "1". - Priority Level (PRL, 3 bits). These bits define the current priority level, PRL=0: the highest priority, PRL=7: the lowest priority (the interrupt cannot be acknowledged) - Interrupt Vector Register (IVR, up to 7 bits). The IVR points to the vector table which itself contains the interrupt routine start address.
WATCHDOG ENABLE WDEN
CORE RESET TLIP MUX
WATCHDOG TIMER END OF COUNT
PENDING MASK
TOP LEVEL INTERRUPT REQUEST
NMI
IMC
OR TLIS
TLTEV TLNM TLI IEN
VA00294
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3.9 NMI/WKP0 LINE MANAGEMENT In the ST92141, the Non Maskable Interrupt (NMI) and the Wake Up 0 line (WKUP0) functionalities are both physically mapped on the same I/O Port pin P5.1 (refer to Section 1.2). The NMI/WKUP0 is a single alternate function Input, associated with pin P5.1. It is input to the InFigure 24. NMI/WKUP0 Line Management duction Motor Controller (IMC) and the Wake Up Management Unit (WUIMU). The IMC Controller processes the NMI Input and generates the Non Maskable Interrupt request to the CPU (refer to Figure 24 and IMC Figure 71).
UH/UL/VH VL/WH/WL
Output Buffers IMC NMI
P5.1
Input Buffer
NMI/WKUP0 NMI to CPU
CPU
WKUP0 WUIMU
Stop request to RCCU
NMI Event Handling To enable an NMI event on the NMI/WKUP0 line, the following bits must be programmed: - TLNM bit in the NICR register, - TLI and IEN bits in the CICR register - NMI bit in the IMCIVR register - NMIL bit in the PBR register - NMIE bit in the PCR1 register An event on the NMI/WKUP0 line is handled by the ST92141 in the following way: - a NMI event is acknowledged in the CPU only when the internal clock INTCLK is running (i.e. when the ST92141 is not in Stop Mode). - a NMI event is immediately acknowledged in the IMC. The ST92141 can be either in Stop or in
Run Mode (the NMI/WKUP0 line is detected asynchronously). Wake-up Event Handling To enable a wake-up event on the NMI/WKUP0 line, the following bits must be programmed: - WUMx bits in the WUMRL register - WUTx bits in the WUTRL register An event on the NMI/WKUP0 or the WKUP[3:1] lines is handled by the ST92141 in the following way: - a wake up event of one external line (out of the four available), is immediately acknowledged in the WUIMU. The ST92141 can be either in Stop or in Run mode (the NMI/WKUP0 and WKUP[3:1] lines are detected asynchronously).
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NMI/WKP0 LINE MANAGEMENT (Cont'd) 3.9.1 NMI/Wake-Up Event Handling in Run mode The four external lines WKUP0/NMI, WKUP1-3 can also be used when the device is in Run Mode. In addition, if the WKUP0/NMI line is used and the NMI and WKUP0 events are enabled by programming the CPU, IMC and WUIMU registers, a transition on the input pin can generate the following events: - IMC: the six output phases UH/UL/VH/VL/WH/ WL are released in High Impedance. The NMI bit of the IMCIVR register is automatically set to "1". A non maskable interrupt request is then sent to the CPU. - CPU: the NMI pending bit of the CICR register is set and the corresponding NMI interrupt routine is immediately executed. Note 1: The NMI pending bits of the IMCIVR register must be cleared by software in the NMI routine, whereas the NMI pending bit of the CICR register is cleared by hardware when NMI routine is acknowledged. Note 2: The external NMI/WKUP0 event is flagged in the NMI pending bit of the IMCIVR register. The NMI routine must clear this bit. This operation must occur after disactivation of the NMI/WKUP0 line (otherwise, the next NMI/WKUP0 event will be lost, if the CPU is sensitive to a rising edge on the NMI input). The flexibility of the ST9 also allows the use of the NMI/WKUP0 line as a wake up function only or as a Non Maskable Interrupt only. WARNING: 1. The NMI management implemented in the ST92141 imposes the following constraints on the P5.3 (NMI/WKUP0) I.O pin: - No glitches should occur on the pin to avoid unintentional NMI/wake up requests. - A minimum pulse width is requested for the pin activation (refer to ST92141 Electrical Specification). 2. The WKUP0-3 management implemented in the ST92141 imposes the following constraints on the P5.0 (WKUP1), P5.2 (WKUP0), P3.2 (WKUP3) and P3.6 (WKUP2):
- No glitches should occur on WKUP0-3 pins to avoid unintentional requests. 3.9.2 NMI/Wake-Up Event Handling in STOP mode The ST92141 enters Stop Mode by software writing a special Stop bit setting sequence in the WUCTRL register of the WUIMU. After entering Stop Mode, the device can be woken up by one of the four Wake Up external lines (refer to Section 3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU). In addition, if the WKUP0/NMI line is used and the NMI and WKUP0 events are enabled by programming the CPU, IMC and WUIMU registers, a transition on the input pin can generate the following events: - IMC: the six output phases UH/UL/VH/VL/WH/ WL are released in High Impedance. The NMI bit of the IMCIVR register is automatically set to "1". A non maskable interrupt request is then sent to the CPU. - WUIMU: the NMI/WKUP0 activation wakes up the ST92141 from Stop mode, allowing the CPU to acknowledge the NMI request from IMC - CPU: the NMI pending bit of the CICR register is set and the corresponding NMI interrupt routine is executed as soon as the ST92141 is exited from Stop mode. Note: The NMI pending bits of the IMCIVR register must be cleared by software in the NMI routine, whereas the NMI pending bit of the CICR register is cleared by hardware when the NMI routine is acknowledged. 3.9.3 Unused Wake Up Management Unit lines The WUIMU can manage up to 16 External-Interrupt/ Wake up lines. Usually, only a subset of these 16 lines is used. In the ST92141, 4 lines out of 16 are available as external lines (WKUP0/1/2/3) but the Pending and Mask bits of the unused lines (WKUP4 to WKUP 15) are also accessible by software (refer to Section 3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)). Therefore, it is possible to generate a software interrupt by disabling the Mask and by setting the Pending bit of an unused channel.
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3.10 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions completely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. If the interrupt request comes from an external pin, the trigger event must occur a minimum of one INTCLK cycle before the sampling time. When an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immediately and the interrupt request is serviced; if not, the CPU waits until the current instruction is terminated and then services the request. Instruction execution can normally be aborted provided no write operation has been performed. For an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a maximum of 55 clock cycles (DIV instruction), 53 clock
cycles (DIVWS and MUL instructions) or 49 for other instructions. For a non-maskable Top Level interrupt, the response time between a user event and the start of the interrupt service routine can range from a minimum of 22 clock cycles to a maximum of 51 clock cycles (DIV instruction), 49 clock cycles (DIVWS and MUL instructions) or 45 for other instructions. In order to guarantee edge detection, input signals must be kept low/high for a minimum of one INTCLK cycle. An interrupt machine cycle requires a basic 18 internal clock cycles (CPUCLK), to which must be added a further 2 clock cycles if the stack is in the Register File. 2 more clock cycles must further be added if the CSR is pushed (ENCSR =1). The interrupt machine cycle duration forms part of the two examples of interrupt response time previously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. In Wait for Interrupt mode, a further cycle is required as wake-up delay.
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3.11 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h)
7 GCEN TLIP TLI IEN IAM 0 CPL2 CPL1 CPL0
the IEN bit when interrupts are disabled or when no peripheral can generate interrupts. For example, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequence DI; POP CICR to make sure that no interrupts are being arbitrated when CICR is modified. Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software. 0: Concurrent Mode 1: Nested Mode Bit 2:0 = CPL[2:0]: Current Priority Level. These bits define the Current Priority Level. CPL=0 is the highest priority. CPL=7 is the lowest priority. These bits may be modified directly by the interrupt hardware when Nested Interrupt Mode is used. EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)
7 0
Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit Multifunction Timer peripheral. 0: MFT disabled 1: MFT enabled Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when Top Level Interrupt (TLI) trigger event occurs. It is cleared by hardware when a TLI is acknowledged. It can also be set by software to implement a software TLI. 0: No TLI pending 1: TLI pending Bit 5 = TLI: Top Level Interrupt. This bit is set and cleared by software. 0: A Top Level Interrupt is generated when TLIP is set, only if TLNM=1 in the NICR register (independently of the value of the IEN bit). 1: A Top Level Interrupt request is generated when IEN=1 and the TLIP bit are set. Bit 4 = IEN: Interrupt Enable. This bit is cleared by the interrupt machine cycle (except for a TLI). It is set by the iret instruction (except for a return from TLI). It is set by the EI instruction. It is cleared by the DI instruction. 0: Maskable interrupts disabled 1: Maskable Interrupts enabled Note: The IEN bit can also be changed by software using any instruction that operates on register CICR, however in this case, take care to avoid spurious interrupts, since IEN cannot be cleared in the middle of an interrupt arbitration. Only modify
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
Bit 7 = TED1: INTD1 Trigger Event Bit 6 = TED0: INTD0 Trigger Event Bit 5 = TEC1: INTC1 Trigger Event Bit 4 = TEC0: INTC0 Trigger Event Bit 3 = TEB1: INTB1 Trigger Event Bit 2 = TEB0: INTB0 Trigger Event Bit 1 = TEA1: INTA1 Trigger Event Bit 0 = TEA0: INTA0 Trigger Event These bits are set and cleared by software. 0: Select falling edge as interrupt trigger event 1: Select rising edge as interrupt trigger event
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)
7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 0 IPA1 IPA0
Bit 3 = IMB1: INTB1 Interrupt Mask Bit 2 = IMB0: INTB0 Interrupt Mask Bit 1 = IMA1: INTA1 Interrupt Mask Bit 0 = IMA0: INTA0 Interrupt Mask These bits are set and cleared by software. 0: Interrupt masked 1: Interrupt not masked (an interrupt is generated if the IPxx and IEN bits = 1) EXTERNAL INTERRUPT PRIORITY REGISTER (EIPLR) R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)
7
Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = IPD0: INTD0 Interrupt Pending bit Bit 5 = IPC1: INTC1 Interrupt Pending bit Bit 4 = IPC0: INTC0 Interrupt Pending bit Bit 3 = IPB1: INTB1 Interrupt Pending bit Bit 2 = IPB0: INTB0 Interrupt Pending bit Bit 1 = IPA1: INTA1 Interrupt Pending bit Bit 0 = IPA0: INTA0 Interrupt Pending bit These bits are set by hardware on occurrence of a trigger event (as specified in the EITR register) and are cleared by hardware on interrupt acknowledge. They can also be set by software to implement a software interrupt. 0: No interrupt pending 1: Interrupt pending EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR) R244 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)
7 0
LEVEL
0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
Bit 7:6 = PL2D, PL1D: INTD0, D1 Priority Level. Bit 5:4 = PL2C, PL1C: INTC0, C1 Priority Level. Bit 3:2 = PL2B, PL1B: INTB0, B1 Priority Level. Bit 1:0 = PL2A, PL1A: INTA0, A1 Priority Level. These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by hardware at 0 for Channels A0, B0, C0 and D0 and at 1 for Channels A1, B1, C1 and D1.
PL2x 0 0 PL1x 0 1 0 1 Hardware bit 0 1 0 1 0 1 0 1 Priority 0 (Highest) 1 2 3 4 5 6 7 (Lowest)
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0 1
Bit 7 = IMD1: INTD1 Bit 6 = IMD0: INTD0 Bit 5 = IMC1: INTC1 Bit 4 = IMC0: INTC0
Interrupt Mask Interrupt Mask Interrupt Mask Interrupt Mask
1
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h)
7 V7 V6 V5 V4 0 TLTEV TLIS IAOS EWEN
0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external memory access cycle). Note: For more details on Wait mode refer to the section describing the WAITN pin in the External Memory Chapter. NESTED INTERRUPT CONTROL (NICR) R247 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)
7 TLNM HL6 HL5 HL4 HL3 HL2 HL1 0 HL0
Bit 7:4 = V[7:4]: Most significant nibble of External Interrupt Vector. These bits are not initialized by reset. For a representation of how the full vector is generated from V[7:4] and the selected external interrupt channel, refer to Figure 22. Bit 3 = TLTEV: Top Level Trigger Event bit. This bit is set and cleared by software. 0: Select falling edge as NMI trigger event 1: Select rising edge as NMI trigger event Bit 2 = TLIS: Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source Bit 1 = IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Bit 0 = EWEN: External Wait Enable. This bit is set and cleared by software.
Bit 7 = TLNM: Top Level Not Maskable. This bit is set by software and cleared only by a hardware reset. 0: Top Level Interrupt Maskable. A top level request is generated if the IEN, TLI and TLIP bits =1 1: Top Level Interrupt Not Maskable. A top level request is generated if the TLIP bit =1 Bit 6:0 = HL[6:0]: Hold Level x These bits are set by hardware when, in Nested Mode, an interrupt service routine at level x is interrupted from a request with higher priority (other than the Top Level interrupt request). They are cleared by hardware at the iret execution when the routine at level x is recovered.
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3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 3.12.1 Introduction 3.12.2 Main Features s Supports up to 16 additional external wake-up The Wake-up/Interrupt Management Unit extends or interrupt lines the number of external interrupt lines from 8 to 23 (depending on the number of external interrupt s Wake-Up lines can be used to wake-up the ST9 lines mapped on external pins of the device). It alfrom STOP mode. lows the source of the INTD1 external interrupt s Programmable selection of wake-up or interrupt channel to be used for up to 16 additional external s Programmable wake-up trigger edge polarity Wake-up/interrupt pins. s All Wake-Up Lines maskable These 16 WKUP pins can be programmed as exNote: The number of available pins is device deternal interrupt lines or as wake-up lines, able to pendent. Refer to the device pinout description. exit the microcontroller from low power mode (STOP mode) (see Figure 25). Figure 25. Wake-Up Lines / Interrupt Management Unit Block Diagram
WKUP[7:0] WKUP[15:8]
WUTRL
WUTRH TRIGGERING LEVEL REGISTERS
WUPRL
WUPRH PENDING REQUEST REGISTERS
WUMRL
WUMRH MASK REGISTERS
Set Reset
Note: Reset Signal on stop bit is stronger than the set signal
INT7 (not connected) SW SETTING 1 0
WUCTRL
STOP ID1S WKUP-INT
TO CPU INTD1 - External Interrupt Channel
TO RCCU - Stop Mode Control
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) 3.12.3 Functional Description 7. Write the sequence 1,0,1 to the STOP bit of the WUCTRL register with three consecutive write 3.12.3.1 Interrupt Mode operations. This is the STOP bit setting To configure the 16 wake-up lines as interrupt sequence. sources, use the following procedure: To detect if STOP Mode was entered or not, im1. Configure the mask bits of the 16 wake-up lines mediately after the STOP bit setting sequence, (WUMRL, WUMRH). poll the RCCU EX_STP bit (R242.7, Page 55) and the STOP bit itself. 2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH). 3. Set bit 7 of EIMR (R244 Page 0) and EITR 3.12.3.3 STOP Mode Entry Conditions (R242 Page 0) registers of the CPU: so an Assuming the ST9 is in Run mode: during the interrupt coming from one of the 16 lines can be STOP bit setting sequence the following cases correctly acknowledged. may occur: 4. Reset the WKUP-INT bit in the WUCTRL regisCase 1: Wrong STOP bit setting sequence ter to disable Wake-up Mode. This can happen if an Interrupt/DMA request is ac5. Set the ID1S bit in the WUCTRL register to disknowledged during the STOP bit setting seable the INT7 external interrupt source and quence. In this case polling the STOP and enable the 16 wake-up lines as external interEX_STP bits will give: rupt source lines. STOP = 0, EX_STP = 0 To return to standard mode (INT7 external interrupt source enabled and 16 wake-up lines disaThis means that the ST9 did not enter STOP mode bled) it is sufficient to reset the ID1S bit. due to a bad STOP bit setting sequence: the user must retry the sequence. Case 2: Correct STOP bit setting sequence 3.12.3.2 Wake-up Mode Selection In this case the ST9 enters STOP mode. To configure the 16 lines as wake-up sources, use the following procedure: To exit STOP mode, a wake-up interrupt must be acknowledged. That implies: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH). STOP = 0, EX_STP = 1 2. Configure the triggering edge registers of the This means that the ST9 entered and exited STOP wake-up lines (WUTRL, WUTRH). mode due to an external wake-up line event. 3. Set, as for Interrupt Mode selection, bit 7 of EIMR and EITR registers only if an interrupt Case 3: A wake-up event on the external wakeroutine is to be executed after a wake-up event. up lines occurs during the STOP bit setting seOtherwise, if the wake-up event only restarts quence the execution of the code from where it was There are two possible cases: stopped, the INTD1 interrupt channel must be masked or the external source must be 1. Interrupt requests to the CPU are disabled: in selected by resetting the ID1S bit. this case the ST9 will not enter STOP mode, no interrupt service routine will be executed and 4. Since the RCCU can generate an interrupt the program execution continues from the request when exiting from STOP mode, take instruction following the STOP bit setting care to mask it even if the wake-up event is sequence. The status of STOP and EX_STP only to restart code execution. bits will be again: 5. Set the WKUP-INT bit in the WUCTRL register STOP = 0, EX_STP = 0 to select Wake-up Mode. 6. Set the ID1S bit in the WUCTRL register to disThe application can determine why the ST9 did able the INT7 external interrupt source and not enter STOP mode by polling the pending enable the 16 wake-up lines as external interbits of the external lines (at least one must be at rupt source lines. This is not mandatory if the 1). wake-up event does not require an interrupt response.
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) 2. Interrupt requests to CPU are enabled: in this 3.12.4.1 Procedure for Entering/Exiting STOP case the ST9 will not enter STOP mode and the mode interrupt service routine will be executed. The 1. Program the polarity of the trigger event of status of STOP and EX_STP bits will be again: external wake-up lines by writing registers STOP = 0, EX_STP = 0 WUTRH and WUTRL. 2. Check that at least one mask bit (registers The interrupt service routine can determine why WUMRH, WUMRL) is equal to 1 (so at least the ST9 did not enter STOP mode by polling one external wake-up line is not masked). the pending bits of the external lines (at least one must be at 1). 3. Reset at least the unmasked pending bits: this allows a rising edge to be generated on the INTD1 channel when the trigger event occurs If the MCU really exits from STOP Mode, the (an interrupt on channel INTD1 is recognized RCCU EX_STP bit is still set and must be reset by when a rising edge occurs). software. Otherwise, if an Interrupt/DMA request 4. Select the interrupt source of the INTD1 chanwas acknowledged during the STOP bit setting senel (see description of ID1S bit in the WUCTRL quence, the RCCU EX_STP bit is reset. This register) and set the WKUP-INT bit. means that the MCU has filtered the STOP Mode entry request. 5. To generate an interrupt on channel INTD1, bits EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7, The WKUP-INT bit can be used by an interrupt Page 0) must be set and bit EIPR.7 must be routine to detect and to distinguish events coming reset. Bits 7 and 6 of register R245, Page 0 from Interrupt Mode or from Wake-up Mode, allowmust be written with the desired priority level for ing the code to execute different procedures. interrupt channel INTD1. To exit STOP mode, it is sufficient that one of the 6. Reset the STOP bit in register WUCTRL and 16 wake-up lines (not masked) generates an the EX_STP bit in the CLK_FLAG register event: the clock restarts after the delay needed for (R242.7, Page 55). Refer to the RCCU chapter. the oscillator to restart. 7. To enter STOP mode, write the sequence 1, 0, 1 to the STOP bit in the WUCTRL register with Note: After exiting from STOP Mode, the software three consecutive write operations. can successfully reset the pending bits (edge sen8. The code to be executed just after the STOP sitive), even though the corresponding wake-up sequence must check the status of the STOP line is still active (high or low, depending on the and RCCU EX_STP bits to determine if the ST9 Trigger Event register programming); the user entered STOP mode or not (See "Wake-up must poll the external pin status to detect and disMode Selection" on page 56. for details). If the tinguish a short event from a long one (for example ST9 did not enter in STOP mode it is necessary keyboard input with keystrokes of varying length). to reloop the procedure from the beginning, otherwise the procedure continues from next point. 9. Poll the wake-up pending bits to determine 3.12.4 Programming Considerations which wake-up line caused the exit from STOP mode. The following paragraphs give some guidelines for designing an application program. 10.Clear the wake-up pending bit that was set.
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ST92141 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) - Reset WUPRH register using a read-modifywrite instruction (AND, BRES, BAND) 3.12.4.2 Simultaneous Setting of Pending Bits - Clear the EIPR.7 bit It is possible that several simultaneous events set - Reset the WUPRL register using a read-moddifferent pending bits. In order to accept subseify-write instruction (AND, BRES, BAND) quent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this 2. The user chooses to keep at least one pending operation allows a rising edge to be generated on bit active: at least one additional interrupt the INTD1 line (if there is at least one more pendrequest will be generated on the INTD1 chaning bit set and not masked) and so to set EIPR.7 nel. In this case the user has to reset the bit again. A further interrupt on channel INTD1 will desired pending bits with a read-modify-write be serviced depending on the status of bit EIMR.7. instruction (AND, BRES, BAND). This operation Two possible situations may arise: will generate a rising edge on the INTD1 channel and the EIPR.7 bit will be set again. An 1. The user chooses to reset all pending bits: no interrupt on the INTD1 channel will be serviced further interrupt requests will be generated on depending on the status of EIMR.7 bit. channel INTD1. In this case the user has to: - Reset EIMR.7 bit (to avoid generating a spurious interrupt request during the next reset operation on the WUPRH register)
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ST92141 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) enter STOP mode: the user must re-enter the se3.12.5 Register Description quence to set the STOP bit. WAKE-UP CONTROL REGISTER (WUCTRL) WARNING: Whenever a STOP request is issued R249 - Read/Write to the MCU, a few clock cycles are needed to enter Register Page: 57 STOP mode (see RCCU chapter for further deReset Value: 0000 0000 (00h) tails). Hence the execution of the instruction fol7 0 lowing the STOP bit setting sequence might start before entering STOP mode: if such instruction STOP ID1S WKUP-INT performs a register write operation, the ST9 will not enter in STOP mode. In order to avoid to execute register write instructions after a correct Bit 2 = STOP: Stop bit. STOP bit setting sequence and before entering To enter STOP Mode, write the sequence 1,0,1 to the STOP mode, it is mandatory to execute 3 NOP this bit with three consecutive write operations. instructions after the STOP bit setting sequence. When a correct sequence is recognized, the STOP bit is set and the RCCU puts the MCU in STOP Mode. The software sequence succeeds Bit 1 = ID1S: Interrupt Channel INTD1 Source. only if the following conditions are true: This bit is set and cleared by software. - The WKUP-INT bit is 1, 0: INT7 external interrupt source selected, excluding wake-up line interrupt requests - All unmasked pending bits are reset, 1: The 16 external wake-up lines enabled as inter- At least one mask bit is equal to 1 (at least one rupt sources, replacing the INT7 external pin external wake-up line is not masked). function Otherwise the MCU cannot enter STOP mode, the WARNING: To avoid spurious interrupt requests program code continues executing and the STOP on the INTD1 channel due to changing the interbit remains cleared. rupt source, do the following before modifying the The bit is reset by hardware if, while the MCU is in ID1S bit: STOP mode, a wake-up interrupt comes from any 1. Mask the INTD1 interrupt channel (bit 7 of regof the unmasked wake-up lines. The STOP bit is at ister EIMR - R244, Page 0 - reset to 0). 1 in the two following cases (See "Wake-up Mode 2. Program the ID1S bit as needed. Selection" on page 56. for details): 3. Clear the IPD1 interrupt pending bit (bit 7 of - After the first write instruction of the sequence (a register EIPR - R243, Page 0). 1 is written to the STOP bit) 4. Remove the mask on INTD1 (bit EIMR.7=1). - At the end of a successful sequence (i.e. after the third write instruction of the sequence) WARNING: Writing the sequence 1,0,1 to the Bit 0 = WKUP-INT: Wakeup Interrupt. STOP bit will enter STOP mode only if no other This bit is set and cleared by software. register write instructions are executed during the 0: The 16 external wakeup lines can be used to sequence. If Interrupt or DMA requests (which algenerate interrupt requests ways perform register write operations) are ac1: The 16 external wake-up lines to work as wakeknowledged during the sequence, the ST9 will not up sources for exiting from STOP mode
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ST92141 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) WAKE-UP MASK REGISTER LOW (WUMRL) WAKE-UP MASK REGISTER HIGH (WUMRH) R251 - Read/Write R250 - Read/Write Register Page: 57 Register Page: 57 Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7
WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9
0
WUM8
7
WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1
0
WUM0
Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the corresponding WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: - If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are generated. - If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. - If ID1S=0 and WKUP-INT=1 only a wake-up event is generated. - If ID1S=0 and WKUP-INT=0 neither interrupts on channel INTD1 nor wake-up events are generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7. If WUMx is reset, no wake-up events can be generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0).
Bit 7:0 = WUM[7:0]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the corresponding WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then: - If ID1S=1 and WKUP-INT=1 then an interrupt on channel INTD1 and a wake-up event are generated. - If ID1S=1 and WKUP-INT=0 only an interrupt on channel INTD1 is generated. - If ID1S=0 and WKUP-INT=1 only a wake-up event is generated. - If ID1S=0 and WKUP-INT=0 neither interrupts on channel INTD1 nor wake-up events are generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7. If WUMx is reset, no wake-up events can be generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0).
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ST92141 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont'd) WAKE-UP TRIGGER REGISTER HIGH (WUTRH) WAKE-UP PENDING REGISTER HIGH R252 - Read/Write (WUPRH) Register Page: 57 R254 - Read/Write Reset Value: 0000 0000 (00h) Register Page: 57 7 0 Reset Value: 0000 0000 (00h)
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8
7
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9
0
WUP8
Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity Bits These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set on the falling edge of the input wake-up line. 1: The corresponding WUPx pending bit will be set on the rising edge of the input wake-up line. WAKE-UP TRIGGER REGISTER LOW (WUTRL) R253 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)
7
WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1
Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by software. They can be set by software to implement a software interrupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occurred
0
WUT0
WAKE-UP PENDING REGISTER LOW (WUPRL) R255 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)
7 0
WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0
Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set on the falling edge of the input wake-up line. 1: The corresponding WUPx pending bit will be set on the rising edge of the input wake-up line. WARNING 1. As the external wake-up lines are edge triggered, no glitches must be generated on these lines. 2. If either a rising or a falling edge on the external wake-up lines occurs while writing the WUTRH or WUTRL registers, the pending bit will not be set.
WUP7
Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by software. They can be set by software to implement a software interrupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occurred Note: To avoid losing a trigger event while clearing the pending bits, it is recommended to use read-modify-write instructions (AND, BRES, BAND) to clear them.
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ST92141 - EM CONFIGURATION REGISTERS (EM)
4 EM CONFIGURATION REGISTERS (EM)
In ST9 devices with external memory, the EM registers (External Memory Registers) are used to configure the external memory interface. In the ST92141, only the BSZ, ENCSR and DPREM bits must be programmed. All other bits in these registers must be left at their reset values. EM REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h)
7 1 0 0 0 0 0 BSZ 0 0
Bit 7:2 = Reserved. Bit 1 = BSZ: Buffer size. 0: I/O ports P3.6, P3.5, P5.0, P5.2 use output buffers with standard current capability (less noisy). 1: I/O ports P3.6, P3.5, P5.0, P5.2 use output buffers with high current capability (more noisy) Bit 0 = Reserved. EM REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh)
7 0 ENCSR DPREM 0 1 1 1 0 1
the ST9 CPU behaviour whenever an interrupt request is issued. 0: The CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. 1: ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. Bit 5 = DPRREM: Data Page Registers remapping 0: The locations of the four MMU (Memory Management Unit) Data Page Registers (DPR0, DPR1, DPR2 and DPR3) are in page 21. 1: The four MMU Data Page Registers are swapped with that of the Data Registers of ports 0-3. Refer to Figure 11 Bit 4:0 = Reserved, keep in reset state.
Bit 7 = Reserved, keep in reset state. Bit 6 = ENCSR: Enable Code Segment Register. This bit is set and cleared by software. It affects
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5 RESET AND CLOCK CONTROL UNIT (RCCU)
5.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) comprises two distinct sections: - the Clock Control Unit, which generates and manages the internal clock signals. - the Reset/Stop Manager, which detects and flags Hardware, Software and Watchdog generated resets. In Stop mode and Halt mode, all oscillators are frozen in order to achieve the lowest possible power consumption. Entering and exiting Stop mode is controlled by the WUIMU. Halt mode is entered by executing the HALT instruction. Halt mode can only be exited by a reset event. 5.2 CLOCK CONTROL UNIT The Clock Control Unit generates the internal clocks for the CPU core (CPUCLK) and for the onchip peripherals (INTCLK). The Clock Control Unit may be driven by an external crystal circuit, connected to the OSCIN and OSCOUT pins, or by an external pulse generator, connected to OSCIN (see Figure 34 and Figure 36). If present, another clock source named CK_AF can be provided to the system. Depending on the device, it can be a periodic signal applied to the CK_AF pin or a signal generated internally by the MCU (RC oscillator). 5.2.1 Clock Control Unit Overview As shown in Figure 26, a programmable divider can divide the CLOCK1 input clock signal by two. The resulting signal, CLOCK2, is the reference input clock to the programmable Phase Locked Loop frequency multiplier, which is capable of multiplying the clock frequency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a programmable divider, by a factor of 1 to 7. By this means, the ST9 can operate with cheaper, medium frequency (3-5 MHz) crystals, while still providing a high frequency internal clock for maximum system performance; the range of available multiplication and division factors allow a great number of operating clock frequencies to be derived from a single crystal frequency. The undivided PLL clock is also available for special purposes (high-speed peripheral). For low power operation, especially in Wait for Interrupt mode, the Clock Multiplier unit may be turned off, whereupon the output clock signal may be programmed as CLOCK2 divided by 16. Furthermore, during the execution of a WFI in Low Power mode, the CK_AF clock is automatically divided by 16 for further consumption reduction. (for the selection of this signal refer to the description the CK_AF clock source in the following sections of this chapter). The internal system clock, INTCLK, is routed to all on-chip peripherals, as well as to the programmable Clock Prescaler Unit which generates the clock for the CPU core (CPUCLK). The Clock Prescaler is programmable and can slow the CPU clock by a factor of up to 8, allowing the programmer to reduce CPU processing speed, and thus power consumption, while maintaining a high speed clock to the peripherals. This is particularly useful when little actual processing is being done by the CPU and the peripherals are doing most of the work.
Figure 26. Clock Control Unit Simplified Block Diagram
1/16
PLL
Quartz oscillator
1/2
CLOCK1
CLOCK2
Clock Multiplier /Divider Unit
CPU Clock Prescaler
CPUCLK to CPU Core
1/16
CK_AF pin CK_AF
INTCLK to Peripherals
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Figure 27. ST92141 Clock Distribution Diagram (settings given for 5MHz crystal & 25MHz lnternal clock)
8-bit Prescaler 10-bit PWM Counter
Conversion time N X 138 X INTCLK
N=1,4,6,8,10,12,14,16 1/N
1/2
12-bit Prescaler 16-bit Down Counter 16-bit Down Counter
IMC
A/D
1...256 8-bit Prescaler
1/4 N=2,4,8 16-bit Up Counter 1/N EXTCLKx (Max INTCLK/4)
WDG
1...256 8-bit Prescaler
EFT
25 MHz INTCLK
P5.7
1/4
STIM
1...8 Baud Rate Generator 1/N N=2,4,16,32 3-bit Prescaler 1/2 1...8
SCK Master
CPUCLK
3-bit Prescaler
SCK Slave (Max INTCLK/2)
LOGIC
SPI
CPU
EMBEDDED MEMORY
WFI and LPOWFI=1 and WFI_CKSEL=1 or CKAF_SEL=1 XT_DIV16=1 1/16 CSU_CKSEL=1
0 01
1
RAM EPROM/FASTROM /OTP
DIV2=1
MX1=0 MX0=0 PLL x 10 0 1 1
5 MHz Quartz Oscillator
1/2
0 1
CLOCK2
RCCU
CK_AF CK_AF pin 1/16
1 0
DX2=0 DX1=0 DX0=0
WFI and LPOWFI=1 and WFI_CKSEL = 1
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.3 CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: - MODER (Mode Register) - CLK_FLAG (Clock Flag Register) This is a System Register (R235, Group E). This is a Paged Register (R242, Page 55). The input clock divide-by-two and the CPU clock prescaler factors are handled by this register. - CLKCTL (Clock Control Register) This is a Paged Register (R240, Page 55). The low power modes and the interpretation of the HALT instruction are handled by this register. This register contains various status flags, as well as control bits for clock selection. - PLLCONF (PLL Configuration Register) This is a Paged Register (R246, Page 55). The PLL multiplication and division factors are programmed in this register.
Figure 28. Clock Control Unit Programming
XTSTOP
(CLK_FLAG)
DIV2
(MODER)
CSU_CKSEL
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
1/16
0 0 Quartz oscillator
1/2 CLOCK1 1/16
1
CLOCK2
PLL x 6/8/10/14
0
0 1
INTCLK
to Peripherals and CPU Clock Prescaler
1
1/N
1
1 0
CK_AF pin
CK_AF
WFI and LPOWFI=1 and WFI_CKSEL = 1
MX(1:0)
DX(2:0)
XT_DIV16
CKAF_ST
(PLLCONF)
(CLK_FLAG)
Wait for Interrupt and Low Power Modes: LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode. WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode. XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont'd) 5.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condition), CLOCK2, is equal to CLOCK1 divided by two; if DIV2 is reset, CLOCK2 is identical to CLOCK1. Since the input clock to the Clock Multiplier circuit requires a 50% duty cycle for correct PLL operation, the divide by two circuit should be enabled when a crystal oscillator is used, or when the external clock generator does not provide a 50% duty cycle. In practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the PLL multiplier circuit. A CLOCK1 signal with a semiperiod (high or low) shorter than 40ns is forbidden if the divider by two is disabled. When the PLL is active, it multiplies CLOCK2 by 6, 8, 10 or 14, depending on the status of the MX0 -1 bits in PLLCONF. The multiplied clock is then divided by a factor in the range 1 to 7, determined by the status of the DX0-2 bits; when these bits are programmed to 111, the PLL is switched off. Following a RESET phase, programming bits DX0-2 to a value different from 111 will turn the PLL on. After allowing a stabilisation period for the PLL, setting the CSU_CKSEL bit in the CLK_FLAG Register selects the multiplier clock This peripheral contains a lock-in logic that verifies if the PLL is locked to the CLOCK2 frequency. The bit LOCK in CLK_FLAG register becomes 1 when this event occurs. The maximum frequency allowed for INTCLK is 25MHz for 5V operation, and 12MHz for 3V operation. Care is required, when programming the PLL multiplier and divider factors, not to exceed the maximum permissible operating frequency for INTCLK, according to supply voltage. The ST9 being a static machine, there is no lower limit for INTCLK. However, below 1MHz, A/D converter precision (if present) decreases. 5.3.2 CPU Clock Prescaling The system clock, INTCLK, which may be the output of the PLL clock multiplier, CLOCK2, CLOCK2/ 16 or CK_AF, drives a programmable prescaler which generates the basic time base, CPUCLK, for the instruction executer of the ST9 CPU core. This allows the user to slow down program execution during non processor intensive routines, thus reducing power dissipation.
The internal peripherals are not affected by the CPUCLK prescaler and continue to operate at the full INTCLK frequency. This is particularly useful when little processing is being done and the peripherals are doing most of the work. The prescaler divides the input clock by the value programmed in the control bits PRS2,1,0 in the MODER register. If the prescaler value is zero, no prescaling takes place, thus CPUCLK has the same period and phase as INTCLK. If the value is different from 0, the prescaling is equal to the value plus one, ranging thus from two (PRS2,1,0 = 1) to eight (PRS2,1,0 = 7). The clock generated is shown in Figure 29, and it will be noted that the prescaling of the clock does not preserve the 50% duty cycle, since the high level is stretched to replace the missing cycles. This is analogous to the introduction of wait cycles for access to external memory. When External Memory Wait or Bus Request events occur, CPUCLK is stretched at the high level for the whole period required by the function. Figure 29. CPU Clock Prescaling
INTCLK
PRS VALUE 000 001 010 011 CPUCLK 100 101 110 111 VA00260
5.3.3 Peripheral Clock The system clock, INTCLK, which may be the output of the PLL clock multiplier, CLOCK2, CLOCK2/ 16 or CK_AF, is also routed to all ST9 on-chip peripherals and acts as the central timebase for all timing functions.
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CLOCK MANAGEMENT (Cont'd) 5.3.4 Low Power Modes The user can select an automatic slowdown of clock frequency during Wait for Interrupt operation, thus idling in low power mode while waiting for an interrupt. In WFI operation the clock to the CPU core (CPUCLK) is stopped, thus suspending program execution, while the clock to the peripherals (INTCLK) may be programmed as described in the following paragraphs. An example of Low Power operation in WFI is illustrated in Figure 30. If low power operation during WFI is disabled (LPOWFI bit = 0 in the CLKCTL Register), the CPU CLK is stopped but INTCLK is unchanged. If low power operation during Wait for Interrupt is enabled (LPOWFI bit = 1 in the CLKCTL Register), as soon as the CPU executes the WFI instruction, the PLL is turned off and the system clock will be forced to CLOCK2 divided by 16, or to the external low frequency clock, CK_AF divided by 16 if this has been selected by setting WFI_CKSEL, and providing CKAF_ST is set, thus indicating that the external clock is selected and actually present on the CK_AF pin. The division by 16 is only selected by Hardware after entering Low Power WFI mode. If the external clock source is used, the crystal oscillator may be stopped by setting the XTSTOP bit, providing that the CK_AF clock is present and selected, indicated by CKAF_ST being set. The crys-
tal oscillator will be stopped automatically on entering WFI if the WFI_CKSEL bit has been set. It should be noted that selecting a non-existent CK_AF clock source is impossible, since such a selection requires that the auxiliary clock source be actually present and selected. In no event can a non-existent clock source be selected inadvertently. It is up to the user program to switch back to a faster clock on the occurrence of an interrupt, taking care to respect the oscillator and PLL stabilisation delays, as appropriate.It should be noted that any of the low power modes may also be selected explicitly by the user program even when not in Wait for Interrupt mode, by setting the appropriate bits. 5.3.5 Interrupt Generation System clock selection modifies the CLKCTL and CLK_FLAG registers. The clock control unit generates an external interrupt request when CK_AF and CLOCK2/16 are selected or deselected as system clock source, as well as when the system clock restarts after a stop request (when the STOP MODE feature is available on the specific device). This interrupt can be masked by resetting the INT_SEL bit in the CLKCTL register. In the RCCU the interrupt is generated with a high to low transition (see interrupt and DMA chapters for further information).
Table 14. Summary of Operating Modes using main Crystal Controlled Oscillator
MODE PLL x BY 14 PLL x BY 10 PLL x BY 8 PLL x BY 6 SLOW 1 SLOW 2 WAIT FOR INTERRUPT LOW POWER WAIT FOR INTERRUPT RESET EXAMPLE XTAL=4.4 MHz INTCLK XTAL/2 x (14/D) XTAL/2 x (10/D) XTAL/2 x (8/D) XTAL/2 x (6/D) XTAL/2 XTAL/32 CPUCLK INTCLK/N INTCLK/N INTCLK/N INTCLK/N INTCLK/N INTCLK/N DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI 1 1 1 1 1 1 N-1 N-1 N-1 N-1 N-1 N-1 1 1 1 1 X X 10 00 11 01 X X D-1 D-1 D-1 D-1 111 X X X X X X X XT_DIV16 1 1 1 1 1 0
If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway. XTAL/32 XTAL/2 2.2*10/2 = 11MHz STOP INTCLK 1 1 X 0 X 0 X 00 X 111 1 0 1 1
11MHz
1
0
1
00
001
X
1
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 30. Example of Low Power Mode programming
PROGRAM FLOW Begin
COMMENTS
SYSTEM CLOCK FREQUENCY FQ=5 MHz, Vcc=5 V and T=25C
SET UP AFTER RESET PHASE: DIV2 = 1 XTSTOP = 0 CSU_CKSEL = 0 MX(1:0) = 00 Xtal is selected to restart the PLL quickly PLL multiply factor fixed to 10. Quartz divided by 2
2.5 MHz
DX2-0 000 WAIT CSU_CKSEL Wait for the PLL locking (LOCK->1) WFI_CKSEL 1 XTSTOP 1 LPOWFI 1 User's Program WFI Interrupt Interrupt Routine WAIT XTSTOP 0 WFI status 1
Multiplier divider's factor set to 1, and PLL turned ON PLL is system clock source T1*
CK_AF clock selected when WFI To stop PLL and Xtal when a WFI occurs Low Power Mode enabled 25 MHz
Wait For Interrupt No code is executed until an interrupt is requested Interrupt served while the CK_AF is the system clock To restart Xtal and PLL The system CK switches to Xtal The PLL is locked and becomes the system clock T1* T2** CK_AF 2.5 MHz CK_AF/16
CKAF_SEL <- 0 Main code execution continued CSU_CKSEL<- 1 User's Program End
25 MHz * T1 = PLL lock-in time ** T2 = Quartz oscillator start-up time
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.4 CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h)
7
DIV2 PRS2 PRS1 PRS0 -
CLOCK CONTROL REGISTER (CLKCTL) R240 - Read Write Register Page: 55 Reset Value: 0000 0000 (00h)
0
-
7
INT_SEL -
0
SRESEN CKAF_SEL WFI_CKSEL LPOWFI
*Note: This register contains bits which relate to other functions; these are described in the chapter dealing with Device Architecture. Only those bits relating to Clock functions are described here. Bit 5 = DIV2: OSCIN Divided by 2. This bit controls the divide by 2 circuit which operates on the OSCIN Clock. 0: No division of the OSCIN Clock 1: OSCIN clock is internally divided by 2 Bit 4:2 = PRS[2:0]: Clock Prescaling. These bits define the prescaler value used to prescale CPUCLK from INTCLK. When these three bits are reset, the CPUCLK is not prescaled, and is equal to INTCLK; in all other cases, the internal clock is prescaled by the value of these three bits plus one.
Bit 7 = INT_SEL: Interrupt Selection. 0: Select the external interrupt pin as interrupt source (Reset state) 1: Select the internal RCCU interrupt (see Section 5.3.5) Bit 4:6 = Reserved. Must be kept reset for normal operation. Bit 3 = SRESEN: Software Reset Enable. 0: The HALT instruction turns off the quartz, the PLL and the CCU 1: A Reset is generated when HALT is executed Bit 2 = CKAF_SEL: Alternate Function Clock Select. 0: CK_AF clock not selected 1: Select CK_AF clock Note: To check if the selection has actually occurred, check that CKAF_ST is set. If no clock is present on the CK_AF pin, the selection will not occur. Bit 1 = WFI_CKSEL: WFI Clock Select. This bit selects the clock used during Low power WFI mode if LPOWFI = 1. 0: INTCLK during WFI is CLOCK2/16 1: INTCLK during WFI is CK_AF, further divided by 16, providing it is present. In effect this bit sets CKAF_SEL in WFI mode WARNING: When the CK_AF is selected as Low Power WFI clock but the XTAL is not turned off (R242.4 = 0), after exiting from the WFI, CK_AF will be still selected as system clock. In this case, reset the R240.2 bit to switch back to the XT. Bit 0 = LPOWFI: Low Power mode during Wait For Interrupt. 0: Low Power mode during WFI disabled. When WFI is executed, the CPUCLK is stopped and INTCLK is unchanged 1: The ST9 enters Low Power mode when the WFI instruction is executed. The clock during this state depends on WFI_CKSEL
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont'd) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 1000 after a Watchdog Reset Reset Value: 0010 1000 after a Software Reset Reset Value: 0000 1000 after a Power-On Reset
7
EX_ STP WDG RES SOFT RES XTSTOP XT_ DIV16 CKAF_ ST
Take care, as any operation such as a subsequent AND with 1' or an OR with 0' to the XTSTOP bit will reset it and the oscillator will not be stopped even if CKAF_ST is subsequently set. Bit 3 = XT_DIV16: CLOCK/16 Selection This bit is set and cleared by software. An interrupt is generated when the bit is toggled. 0: CLOCK2/16 is selected and the PLL is off 1: The input is CLOCK2 (or the PLL output depending on the value of CSU_CKSEL) WARNING: After this bit is modified from 0 to 1, take care that the PLL lock-in time has elapsed before setting the CSU_CKSEL bit. Bit 2 = CKAF_ST: (Read Only) If set, indicates that the alternate function clock has been selected. If no clock signal is present on the CK_AF pin, the selection will not occur. If reset, the PLL clock, CLOCK2 or CLOCK2/16 is selected (depending on bit 0). Bit 1= LOCK: PLL locked-in This bit is read only. 0: The PLL is turned off or not locked and cannot be selected as system clock source. 1: The PLL is locked Bit 0 = CSU_CKSEL: CSU Clock Select This bit is set and cleared by software. It also cleared by hardware when: - bits DX[2:0] (PLLCONF) are set to 111; - the quartz is stopped (by hardware or software); - WFI is executed while the LPOWFI bit is set; - the XT_DIV16 bit (CLK_FLAG) is forced to `0'. This prevents the PLL, when not yet locked, from providing an irregular clock. Furthermore, a `0' stored in this bit speeds up the PLL's locking. 0: CLOCK2 provides the system clock 1: The PLL Multiplier provides the system clock. NOTE: Setting the CKAF_SEL bit overrides any other clock selection. Resetting the XT_DIV16 bit overrides the CSU_CKSEL selection (see Figure
0
LOC CSU_ K CKSEL
WARNING: If this register is accessed with a logical instruction, such as AND or OR, some bits may not be set as expected. WARNING: If you select the CK_AF as system clock and turn off the oscillator (bits R240.2 and R242.4 at 1), and then switch back to the XT clock by resetting the R240.2 bit, you must wait for the oscillator to restart correctly. Bit 7 = EX_STP: Stop Mode flag This bit is set by hardware and cleared by software. 0: No Stop condition occurred 1: Stop condition occurred Bit 6 = WDGRES: Watchdog reset flag. This bit is read only. 0: No Watchdog reset occurred 1: Watchdog reset occurred Bit 5 = SOFTRES: Software Reset Flag. This bit is read only. 0: No software reset occurred 1: Software reset occurred (HALT instruction) Bit 4 = XTSTOP: Oscillator Stop Enable. 0: Xtal oscillator stop disabled 1: The Xtal oscillator will be stopped as soon as the CK_AF clock is present and selected, whether this is done explicitly by the user program, or as a result of WFI, if WFI_CKSEL has previously been set to select the CK_AF clock during WFI. WARNING: When the program writes `1' to the XTSTOP bit, it will still be read as 0 and is only set when the CK_AF clock is running (CKAF_ST=1).
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CLOCK CONTROL REGISTERS (Cont'd) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00 x111
7 MX1 MX0 DX2 DX1 0 DX0
Table 15. PLL Multiplication Factors
MX1 1 0 1 0 MX0 0 0 1 1 CLOCK2 x 14 10 8 6
Bit 5:4 = MX[1:0]: PLL Multiplication Factor. Refer to Table 15 PLL Multiplication Factors for multiplier settings. Bit 2:0 = DX[2:0]: PLL output clock divider factor. Refer to Table 16 Divider Configuration for divider settings.
Table 16. Divider Configuration
DX2 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 CK PLL CLOCK/1 PLL CLOCK/2 PLL CLOCK/3 PLL CLOCK/4 PLL CLOCK/5 PLL CLOCK/6 PLL CLOCK/7 CLOCK2 (PLL OFF, Reset State)
Figure 31. RCCU General Timing
PLL turned on by user PLL selected by user
STOP request(*) External RESET Xtal clock Multiplier clock Internal reset Xtal/2 PLL
Xtal/2 INTCLK
PLL
20478xTXtal(**)
PLL 4 xTsys Lock-in time
10239*CLOCK2 PLL Lock-in Quartz time start-up Switch to PLL clock
(*) WUIMU (**) +/- 1 TXtal
Exit from RESET
STOP Acknowledged
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Figure 32. RCCU Timing during STOP (CK_AF System Clock)
CKAF_SEL<-1
STOP request (*) Xtal clock CK_AF clock INTCLK
20478 x TXtal(**) Exit from RESET (*) from WUIMU (**) +/- 1 TXtal CK_AF selected 4 xT sys STOP Acknowledged
10239*CLOCK2 Quartz start-up
Figure 33. Low Power WFI Mode with a Stopped Quartz Oscillator
WFI state Xtal clock Multiplier clock CK_AF clock PLL (Tsys =16* TCK_AF) (Tsys = TCK_AF) Tsys=2 xTXtal PLLl XTSTOP<-0 CKAF_SEL<-0 CSU_CKSEL<-1
INTCLK
Xtal's restart time PLL Lock-in time
With: DIV2=1
Interrupt
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.5 OSCILLATOR CHARACTERISTICS The on-chip oscillator circuit uses an inverting gate circuit with tri-state output. Notes: Owing to the Q factor required, Ceramic Resonators may not provide a reliable oscillator source. OSCOUT must not be directly used to drive external circuits. When the oscillator is stopped, OSCOUT goes high impedance. The parallel resistor, R, is disconnected and the oscillator is disabled, forcing the internal clock, CLOCK1, to a high level, and OSCOUT to a high impedance state. To exit the HALT condition and restart the oscillator, an external RESET pulse is required. It should be noted that, if the Watchdog function is enabled, a HALT instruction will not disable the oscillator. This to avoid stopping the Watchdog if a HALT code is executed in error. When this occurs, the CPU will be reset when the Watchdog times out or when an external reset is applied. Figure 34. Crystal Oscillator
CRYSTAL CLOCK R ST9 RIN OSCOUT OSCIN OSCOUT
VR02086A
Table 17. Crystal Specification (5V)
Rs max (ohm) Freq.= 3 MHz Freq.= 4 MHz Freq.= 5 MHz CL1=CL2= CL1=CL2= CL1=CL2= 56pF 47pF 22pF 270 150 110 350 200 120 850 510 340
Legend: CL1, CL2: Maximum Total Capacitances on pins OSCIN and OSCOUT (the value includes the external capacitance tied to the pin CL1 and CL2 plus the parasitic capacitance of the board and of the device). Note: The tables are relative to the fundamental quartz crystal only (not ceramic resonator).
Figure 35. Internal Oscillator Schematic
HALT
ROUT
OSCIN
CL1
CL2
Figure 36. External Clock
VR02116A
1M* *Recommended for oscillator stability
EXTERNAL CLOCK
ST9 OSCIN OSCOUT NC CLOCK INPUT
VR02116B
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: - A Hardware reset, initiated by a low level on the Reset pin. - A Software reset, initiated by a HALT instruction (when enabled). - A Watchdog end of count condition. The Low Voltage Detector (LVD) (see Section 5.8) generates a reset when: - the power supply, when rising, is under the LVD VLVDR Threshold. - the power supply, when falling, is under the LVD VLVDF Threshold. The event which caused the last Reset is flagged in the CLK_FLAG register, by setting the SOFTRES or the WDGRES bits respectively; a hardware initiated reset will leave both these bits reset. The hardware reset overrides all other conditions and forces the ST9 to the reset state. During Reset, the internal registers are set to their reset values, where these are defined, and the I/O pins are set to the Bidirectional Weak Pull-up mode. Reset is asynchronous: as soon as the reset pin is driven low, a Reset cycle is initiated.
Figure 37. Oscillator Start-up Sequence and Reset Timing
VDD MAX VDD MIN TSTART-UP
OSCIN OSCOUT
RESET PIN
TINTCLK 5.1 ms (*)
INTCLK
(*) with 4 MHz quartz
VR02085A
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RESET/STOP MANAGER (Cont'd) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, 55h) written to the appropriate register. The input pin RESET is not driven low by the onchip reset generated by the Timer/Watchdog. When the Reset pin goes high again, a delay occurs before exiting the Reset state. Subsequently a short Boot routine is executed from the device internal Boot ROM, and control then passes to the user program. The Boot routine sets the device characteristics and loads the correct values in the Memory Management Unit's pointer registers, so that these point to the physical memory areas as mapped in the specific device. The precise duration of this short Boot routine varies from device to device, depending on the Boot ROM contents. At the end of the Boot routine the Program Counter will be set to the location specified in the Reset Vector located in the lowest two bytes of memory. 5.6.1 Reset Pin Timing To improve the noise immunity of the device, the Reset pin has a Schmitt trigger input circuit with hysteresis. In addition, a filter will prevent an unwanted reset in case of a single glitch of less than 50 ns on the Reset pin. The device is certain to reset if a negative pulse of more than 20s is ap-
plied. When the reset pin goes high again, a delay of up to 4s will elapse before the RCCU detects this rising front. From this event on, 20478 (about 5 ms with a 4MHz quartz) oscillator clock cycles (CLOCK1) are counted before exiting the Reset state (+-1 CLOCK1 period depending on the delay between the positive edge the RCCU detects and the first rising edge of CLOCK1) If the ST9 is a ROMLESS version, without on-chip program memory, the memory interface ports are set to external memory mode (i.e Alternate Function) and the memory accesses are made to external Program memory with wait cycles insertion. Figure 38. Recommended Signal to be Applied on Reset Pin
VRESET VCC 0.7 VCC 0.3 VCC
20 s Minimum
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5.7 STOP MODE Under control of the Wake-up Interrupt Management Unit (WUIMU), the Reset/Stop Manager can also stop all oscillators without resetting the device. In Stop Mode all context information will be preserved. During this condition the internal clock will be frozen in the high state. Stop Mode is entered by programming the WUIMU registers (See "WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)" on page 55.). An Table 18. Internal Registers Reset Values
Register Number F E D C B A 9 8 7 6 5 4 3 2 1 0 System Register (SSPLR) (SSPHR) (USPLR) (USPHR) (MODER) (Page Ptr) (Reg Ptr 1) (Reg Ptr 0) (FLAGR) (CICR) (PORT5) (PORT4) (PORT3) (PORT2) (PORT1) (PORT0)
active transition on an External Wake Up line, exits the chip from Stop Mode and the MCU resumes execution after a delay of between 10239 CLOCK2 periods and 10239 CLOCK2 periods plus the Oscillator Start Up Time. On exiting from Stop mode an interrupt is generated and the EX_STP bit in CLK_FLAG will be set, to indicate to the user program that the machine is exiting from Stop mode.
Reset Value undefined undefined undefined undefined E0h undefined undefined undefined undefined 87h FFh FFh FFh FFh FFh FFh
Page 0 Register Reserved (SPICR) (SPIDR) (WCR) (WDTCR) (WDTPR) (WDTLR) (WDTHR) (NICR) (EIVR) (EIPLR) (EIMR) (EIPR) (EITR) Reserved Reserved
Reset Value
00h undefined 7Fh 12h undefined undefined undefined 00h x2h FFh 00h 00h 00h
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 39. Oscillator Start-up sequence on Exit from Stop Mode
VDD MAX VDD MIN TSTART-UP
OSCIN OSCOUT
STOP disactivation
5.1 ms (*) < TINTCLK < 5.1 ms + TSTART-UP
INTCLK
(*) with 4MHz quartz and RCCU programmed with XT_STOP bit = 1 when read
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.8 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VLVDf reference value. This means that it secures the power-up as well as the power-down keeping the ST9 in reset. The V LVDf reference value for a voltage drop is lower than the V LVDr reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VLVDr when VDD is rising - VLVDf when VDD is falling Figure 40. Low Voltage Detector vs Reset
VDD
The LVD function is illustrated in Figure 40. Provided the minimum VDD value (guaranteed for the oscillator frequency) is below VLVDf, the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
HYSTERISIS
VLVDhyst VLVDr VLVDf
RESET
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ST92141 - I/O PORTS
6 I/O PORTS
6.1 INTRODUCTION ST9 devices feature flexible individually programmable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin allocations. These lines, which are logically grouped as 8-bit ports, can be individually programmed to provide digital input/output and analog input, or to connect input/output signals to the on-chip peripherals as alternate pin functions. All ports can be individually configured as an input, bi-directional, output or alternate function. In addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. Ports configured as open drain must never have voltage on the port pin exceeding VDD (refer to the Electrical Characteristics section). Depending on the specific port, input buffers are software selectable to be TTL or CMOS compatible, however on Schmitt trigger ports, no selection is possible. Figure 41. I/O Register Map
GROUP E FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h GROUP F PAGE 2 Reserved P3C2 P3C1 P3C0 Reserved P2C2 P2C1 P2C0 Reserved P1C2 P1C1 P1C0 Reserved P0C2 P0C1 P0C0 GROUP F PAGE 3 P7DR P7C2 P7C1 P7C0 P6DR P6C2 P6C1 P6C0 Reserved P5C2 P5C1 P5C0 Reserved P4C2 P4C1 P4C0 GROUP F PAGE 43 P9DR P9C2 P9C1 P9C0 P8DR P8C2 P8C1 P8C0
6.2 SPECIFIC PORT CONFIGURATIONS Refer to the Pin Description chapter for a list of the specific port styles and reset values. 6.3 PORT CONTROL REGISTERS Each port is associated with a Data register (PxDR) and three Control registers (PxC0, PxC1, PxC2). These define the port configuration and allow dynamic configuration changes during program execution. Port Data and Control registers are mapped into the Register File as shown in Figure 41. Port Data and Control registers are treated just like any other general purpose register. There are no special instructions for port manipulation: any instruction that can address a register, can address the ports. Data can be directly accessed in the port register, without passing through other memory or "accumulator" locations.
System Registers
E5h E4h E3h E2h E1h E0h
P5DR P4DR P3DR P2DR P1DR P0DR
R229 R228 R227 R226 R225 R224
Reserved
R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240
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ST92141 - I/O PORTS
PORT CONTROL REGISTERS (Cont'd) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROMless devices, and can be redefined under software control. Bidirectional ports without weak pull-ups are set in high impedance during reset. To ensure proper levels during reset, these ports must be externally connected to either V DD or VSS through external pull-up or pull-down resistors. Other reset conditions may apply in specific ST9 devices. 6.4 INPUT/OUTPUT BIT CONFIGURATION By programming the control bits PxC0.n and PxC1.n (see Figure 42) it is possible to configure bit Px.n as Input, Output, Bidirectional or Alternate Function Output, where X is the number of the I/O port, and n the bit within the port (n = 0 to 7). When programmed as input, it is possible to select the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit. This option is not available on Schmitt trigger ports. The output buffer can be programmed as pushpull or open-drain. A weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirectional (except where the weak pull-up option has been permanently disabled in the pin hardware assignment).
Each pin of an I/O port may assume software programmable Alternate Functions (refer to the device Pin Description and to Section 6.5 ALTERNATE FUNCTION ARCHITECTURE). To output signals from the ST9 peripherals, the port must be configured as AF OUT. On ST9 devices with A/D Converter(s), configure the ports used for analog inputs as AF IN. The basic structure of the bit Px.n of a general purpose port Px is shown in Figure 43. Independently of the chosen configuration, when the user addresses the port as the destination register of an instruction, the port is written to and the data is transferred from the internal Data Bus to the Output Master Latches. When the port is addressed as the source register of an instruction, the port is read and the data (stored in the Input Latch) is transferred to the internal Data Bus. When Px.n is programmed as an Input: (See Figure 44). - The Output Buffer is forced tristate. - The data present on the I/O pin is sampled into the Input Latch at the beginning of each instruction execution. - The data stored in the Output Master Latch is copied into the Output Slave Latch at the end of the execution of each instruction. Thus, if bit Px.n is reconfigured as an Output or Bidirectional, the data stored in the Output Slave Latch will be reflected on the I/O pin.
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INPUT/OUTPUT BIT CONFIGURATION (Cont'd) Figure 42. Control Bits
Bit 7 PxC2 PxC27 Bit n PxC2n Bit 0 PxC20
PxC1
PxC17
PxC1n
PxC10
PxC0
n
PxC07
PxC0n
PxC00
Table 19. Port Bit Configuration Table (n = 0, 1... 7; X = port number)
General Purpose I/O Pins PXC2n PXC1n PXC0n PXn Configuration PXn Output Type PXn Input Type 0 0 0 BID WP OD TTL
(or Schmitt Trigger)
A/D Pins 1 0 1 IN HI-Z TTL 0 1 1 AF OUT PP TTL
(or Schmitt Trigger)
1 0 0 BID OD TTL
(or Schmitt Trigger)
0 1 0 OUT PP TTL
(or Schmitt Trigger)
1 1 0 OUT OD TTL
(or Schmitt Trigger)
0 0 1 IN HI-Z CMOS
(or Schmitt Trigger)
1 1 1 AF OUT OD TTL
(or Schmitt Trigger)
1 1 1 AF IN HI-Z(1) Analog Input
(or Schmitt Trigger)
(1)
For A/D Converter inputs. Port Bit Alternate Function Bidirectional CMOS Standard Input Levels High Impedance Input Open Drain Output Push-Pull TTL Standard Input Levels Weak Pull-up
Legend:
X = n = AF = BID = CMOS= HI-Z = IN = OD = OUT = PP = TTL = WP =
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INPUT/OUTPUT BIT CONFIGURATION (Cont'd) Figure 43. Basic Structure of an I/O Port Pin
I/O PIN
PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP
TTL / CMOS (or Schmitt Trigger)
OUTPUT SLAVE LATCH FROM PERIPHERAL OUTPUT ALTERNATE FUNCTION INPUT OUTPUT BIDIRECTIONAL OUTPUT
TO PERIPHERAL INPUTS AND INTERRUPTS INPUT BIDIRECTIONAL ALTERNATE FUNCTION INPUT LATCH
OUTPUT MASTER LATCH
INTERNAL DATA BUS
Figure 44. Input Configuration
I/O PIN
Figure 45. Output Configuration
I/O PIN
TRISTATE
TTL / CMOS (or Schmitt Trigger) TO PERIPHERAL INPUTS AND INTERRUPTS
OPEN DRAIN PUSH-PULL
TTL (or Schmitt Trigger) TO PERIPHERAL INPUTS AND INTERRUPTS
OUTPUT SLAVE LATCH
OUTPUT SLAVE LATCH
OUTPUT MASTER LATCH
INPUT LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
n n n
INTERNAL DATA BUS
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ST92141 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont'd) When Px.n is programmed as an Output: (Figure 45) - The Output Buffer is turned on in an Open-drain or Push-pull configuration. - The data stored in the Output Master Latch is copied both into the Input Latch and into the Output Slave Latch, driving the I/O pin, at the end of the execution of the instruction. When Px.n is programmed as Bidirectional: (Figure 46) - The Output Buffer is turned on in an Open-Drain or Weak Pull-up configuration (except when disabled in hardware). - The data present on the I/O pin is sampled into the Input Latch at the beginning of the execution of the instruction. - The data stored in the Output Master Latch is copied into the Output Slave Latch, driving the I/ O pin, at the end of the execution of the instruction. WARNING: Due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithmetic/logic and Boolean instructions performed on a bidirectional port pin. These instructions use a read-modify-write sequence, and the result written in the port register depends on the logical level present on the external pin. This may bring unwanted modifications to the port output register content. For example: Port register content, 0Fh external port value, 03h (Bits 3 and 2 are externally forced to 0) A bset instruction on bit 7 will return: Port register content, 83h external port value, 83h (Bits 3 and 2 have been cleared). To avoid this situation, it is suggested that all operations on a port, using at least one bit in bidirectional mode, are performed on a copy of the port register, then transferring the result with a load instruction to the I/O port. When Px.n is programmed as a digital Alternate Function Output: (Figure 47) - The Output Buffer is turned on in an Open-Drain or Push-Pull configuration.
- The data present on the I/O pin is sampled into the Input Latch at the beginning of the execution of the instruction. - The signal from an on-chip function is allowed to load the Output Slave Latch driving the I/O pin. Signal timing is under control of the alternate function. If no alternate function is connected to Px.n, the I/O pin is driven to a high level when in Push-Pull configuration, and to a high impedance state when in open drain configuration. Figure 46. Bidirectional Configuration
I/O PIN
WEAK PULL-UP OPEN DRAIN
TTL (or Schmitt Trigger) TO PERIPHERAL INPUTS AND INTERRUPTS
OUTPUT SLAVE LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
n n
Figure 47. Alternate Function Configuration
I/O PIN
OPEN DRAIN PUSH-PULL
TTL (or Schmitt Trigger) TO PERIPHERAL INPUTS AND INTERRUPTS
OUTPUT SLAVE LATCH
FROM PERIPHERAL OUTPUT INPUT LATCH
INTERNAL DATA BUS
n n n n n n
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6.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: - Data bus Input/Output - Alternate Function Input - Alternate Function Output 6.5.1 Pin Declared as I/O A pin declared as I/O, is connected to the I/O buffer. This pin may be an Input, an Output, or a bidirectional I/O, depending on the value stored in (PxC2, PxC1 and PxC0). 6.5.2 Pin Declared as an Alternate Function Input A single pin may be directly connected to several Alternate Function inputs. In this case, the user must select the required input mode (with the PxC2, PxC1, PxC0 bits) and enable the selected Alternate Function in the Control Register of the peripheral. No specific port configuration is required to enable an Alternate Function input, since the input buffer is directly connected to each alternate function module on the shared pin. As more than one module can use the same input, it is up to the user software to enable the required module as necessary. Parallel I/Os remain operational even when using an Alternate Function input. The exception to this is when an I/O port bit is permanently assigned by hardware as an A/D bit. In this case , after software programming of the bit in AFOD-TTL, the Alternate function output is forced to logic level 1. The analog voltage level on the corresponding pin is directly input to the A/D (See Figure 48). Figure 48. A/D Input Configuration
I/O PIN TOWARDS A/D CONVERTER GND
6.5.3 Pin Declared as an Alternate Function Output The user must select the AF OUT configuration using the PxC2, PxC1, PxC0 bits. Several Alternate Function outputs may drive a common pin. In such case, the Alternate Function output signals are logically ANDed before driving the common pin. The user must therefore enable the required Alternate Function Output by software.
WARNING: When a pin is connected both to an alternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input.
6.6 I/O STATUS AFTER WFI, HALT AND RESET The status of the I/O ports during the Wait For Interrupt, Halt and Reset operational modes is shown in the following table. The External Memory Interface ports are shown separately. If only the internal memory is being used and the ports are acting as I/O, the status is the same as shown for the other I/O ports.
Mode Ext. Mem - I/O Ports P1, P2, P0 P6, P9 High Impedance or next address (depending on Next the last Address memory operation performed on Port) High ImpedNext ance Address I/O Ports
WFI
Not Affected (clock outputs running)
HALT
TRISTATE
RESET
OUTPUT SLAVE LATCH INPUT BUFFER
Not Affected (clock outputs stopped) Bidirectional Weak Alternate function push- Pull-up (High impedance when disapull (ROMless device) bled in hardware).
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
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ST92141 - TIMER/WATCHDOG (WDT)
7 ON-CHIP PERIPHERALS
7.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic description of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to external pins. For the list of WDT pins present on the ST9 device, refer to the device pinout description in the first section of the data sheet. 7.1.1 Introduction The Timer/Watchdog (WDT) peripheral consists of a programmable 16-bit timer and an 8-bit prescaler. It can be used, for example, to: - Generate periodic interrupts - Measure input signal pulse widths - Request an interrupt after a set number of events - Generate an output signal waveform - Act as a Watchdog timer to monitor system integrity Figure 49. Timer/Watchdog Block Diagram
INEN INMD1 INMD2 INPUT & CLOCK CONTROL LOGIC INTCLK/4 OUTMD WROUT OUTEN MUX WDT CLOCK
The main WDT registers are: - Control register for the input, output and interrupt logic blocks (WDTCR) - 16-bit counter register pair (WDTHR, WDTLR) - Prescaler register (WDTPR) The hardware interface consists of up to five signals: - WDIN External clock input - WDOUT Square wave or PWM signal output - INT0 External interrupt input - NMI Non-Maskable Interrupt input - HW0SW1 Hardware/Software Watchdog enable.
WDIN1
WDTPR 8-BIT PRESCALER
WDTRH, WDTRL 16-BIT DOWNCOUNTER
END OF COUNT
NMI 1 INT01 HW0SW11 MUX WDGEN INTERRUPT IAOS TLIS CONTROL LOGIC
OUTPUT CONTROL LOGIC
WDOUT1
RESET TOP LEVEL INTERRUPT REQUEST
1
Pin not present on some ST9 devices.
INTA0 REQUEST
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) 7.1.2 Functional Description 7.1.2.1 External Signals The HW0SW1 pin can be used to permanently enable Watchdog mode. Refer to section 7.1.3.1 on page 87. The WDIN Input pin can be used in one of four modes: - Event Counter Mode - Gated External Input Mode - Triggerable Input Mode - Retriggerable Input Mode The WDOUT output pin can be used to generate a square wave or a Pulse Width Modulated signal. An interrupt, generated when the WDT is running as the 16-bit Timer/Counter, can be used as a Top Level Interrupt or as an interrupt source connected to channel A0 of the external interrupt structure (replacing the INT0 interrupt input). The counter can be driven either by an external clock, or internally by INTCLK divided by 4. 7.1.2.2 Initialisation The prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be loaded with initial values before starting the Timer/Counter. If this is not done, counting will start with reset values. 7.1.2.3 Start/Stop The ST_SP bit enables downcounting. When this bit is set, the Timer will start at the beginning of the following instruction. Resetting this bit stops the counter. If the counter is stopped and restarted, counting will resume from the last value unless a new constant has been entered in the Timer registers (WDTRL, WDTRH). A new constant can be written in the WDTRH, WDTRL, WDTPR registers while the counter is running. The new value of the WDTRH, WDTRL registers will be loaded at the next End of Count (EOC) condition while the new value of the WDTPR register will be effective immediately. End of Count is when the counter is 0. When Watchdog mode is enabled the state of the ST_SP bit is irrelevant.
7.1.2.4 Single/Continuous Mode The S_C bit allows selection of single or continuous mode.This Mode bit can be written with the Timer stopped or running. It is possible to toggle the S_C bit and start the counter with the same instruction. Single Mode On reaching the End Of Count condition, the Timer stops, reloads the constant, and resets the Start/ Stop bit. Software can check the current status by reading this bit. To restart the Timer, set the Start/ Stop bit. Note: If the Timer constant has been modified during the stop period, it is reloaded at start time. Continuous Mode On reaching the End Of Count condition, the counter automatically reloads the constant and restarts. It is stopped only if the Start/Stop bit is reset. 7.1.2.5 Input Section If the Timer/Counter input is enabled (INEN bit) it can count pulses input on the WDIN pin. Otherwise it counts the internal clock/4. For instance, when INTCLK = 24MHz, the End Of Count rate is: 2.79 seconds for Maximum Count (Timer Const. = FFFFh, Prescaler Const. = FFh) 166 ns for Minimum Count (Timer Const. = 0000h, Prescaler Const. = 00h) The Input pin can be used in one of four modes: - Event Counter Mode - Gated External Input Mode - Triggerable Input Mode - Retriggerable Input Mode The mode is configurable in the WDTCR. 7.1.2.6 Event Counter Mode In this mode the Timer is driven by the external clock applied to the input pin, thus operating as an event counter. The event is defined as a high to low transition of the input signal. Spacing between trailing edges should be at least 8 INTCLK periods (or 333ns with INTCLK = 24MHz). Counting starts at the next input event after the ST_SP bit is set and stops when the ST_SP bit is reset.
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) 7.1.2.7 Gated Input Mode This mode can be used for pulse width measurement. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input pin is high, the Timer counts. When it is low, counting stops. The maximum input pin frequency is equivalent to INTCLK/8. 7.1.2.8 Triggerable Input Mode The Timer (clocked internally by INTCLK/4) is started by the following sequence: - setting the Start-Stop bit, followed by - a High to Low transition on the input pin. To stop the Timer, reset the ST_SP bit. 7.1.2.9 Retriggerable Input Mode In this mode, the Timer (clocked internally by INTCLK/4) is started by setting the ST_SP bit. A High to Low transition on the input pin causes counting to restart from the initial value. When the Timer is stopped (ST_SP bit reset), a High to Low transition of the input pin has no effect. 7.1.2.10 Timer/Counter Output Modes Output modes are selected by means of the OUTEN (Output Enable) and OUTMD (Output Mode) bits of the WDTCR register. No Output Mode (OUTEN = "0") The output is disabled and the corresponding pin is set high, in order to allow other alternate functions to use the I/O pin. Square Wave Output Mode (OUTEN = "1", OUTMD = "0") The Timer outputs a signal with a frequency equal to half the End of Count repetition rate on the WDOUT pin. With an INTCLK frequency of 20MHz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 seconds. Pulse Width Modulated Output Mode (OUTEN = "1", OUTMD = "1") The state of the WROUT bit is transferred to the output pin (WDOUT) at the End of Count, and is held until the next End of Count condition. The user can thus generate PWM signals by modifying the status of the WROUT pin between End of Count events, based on software counters decremented by the Timer Watchdog interrupt.
7.1.3 Watchdog Timer Operation This mode is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. The Watchdog, when enabled, resets the MCU, unless the program executes the correct write sequence before expiry of the programmed time period. The application program must be designed so as to correctly write to the WDTLR Watchdog register at regular intervals during all phases of normal operation. 7.1.3.1 Hardware Watchdog/Software Watchdog The HW0SW1 pin (when available) selects Hardware Watchdog or Software Watchdog. If HW0SW1 is held low: - The Watchdog is enabled by hardware immediately after an external reset. (Note: Software reset or Watchdog reset have no effect on the Watchdog enable status). - The initial counter value (FFFFh) cannot be modified, however software can change the prescaler value on the fly. - The WDGEN bit has no effect. (Note: it is not forced low). If HW0SW1 is held high, or is not present: - The Watchdog can be enabled by resetting the WDGEN bit. 7.1.3.2 Starting the Watchdog In Watchdog mode the Timer is clocked by INTCLK/4. If the Watchdog is software enabled, the time base must be written in the timer registers before entering Watchdog mode by resetting the WDGEN bit. Once reset, this bit cannot be changed by software. If the Watchdog is hardware enabled, the time base is fixed by the reset value of the registers. Resetting WDGEN causes the counter to start, regardless of the value of the Start-Stop bit. In Watchdog mode, only the Prescaler Constant may be modified. If the End of Count condition is reached a System Reset is generated.
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) 7.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and counting restarts from the preset value. To reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the WDTLR register between the writing operations. The maximum allowed time between two reloads of the counter depends on the Watchdog timeout period. Figure 50. Watchdog Timer Mode
COUNT VALUE
7.1.3.4 Non-Stop Operation In Watchdog Mode, a Halt instruction is regarded as illegal. Execution of the Halt instruction stops further execution by the CPU and interrupt acknowledgment, but does not stop INTCLK, CPUCLK or the Watchdog Timer, which will cause a System Reset when the End of Count condition is reached. Furthermore, ST_SP, S_C and the Input Mode selection bits are ignored. Hence, regardless of their status, the counter always runs in Continuous Mode, driven by the internal clock. The Output mode should not be enabled, since in this context it is meaningless.
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL WDGEN=0 WRITE AAh,55h INTO WDTRL PRODUCE COUNT RELOAD SOFTWARE FAIL (E.G. INFINITE LOOP) OR PERIPHERAL FAIL
VA00220
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) 7.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is enabled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 selection bit) and TLIS (EIVR.2, Top Level Input Selection bit) allow the selection of 2 interrupt sources (Timer/Watchdog End of Count, or External Pin) handled in two different ways, as a Top Level Non Maskable Interrupt (Software Reset), or as a source for channel A0 of the external interrupt logic. A block diagram of the interrupt logic is given in Figure 51. Note: Software traps can be generated by setting the appropriate interrupt pending bit. Table 20 Interrupt Configuration below, shows all the possible configurations of interrupt/reset sources which relate to the Timer/Watchdog. A reset caused by the watchdog will set bit 6, WDGRES of R242 - Page 55 (Clock Flag Register). See section CLOCK CONTROL REGISTERS.
Figure 51. Interrupt Sources
TIMER WATCHDOG
RESET
WDGEN (WCR.6)
0 MUX INT0 1 IA0S (EIVR.1) INTA0 REQUEST
0 MUX NMI 1 TLIS (EIVR.2) VA00293 TOP LEVEL INTERRUPT REQUEST
Table 20. Interrupt Configuration
Control Bits WDGEN 0 0 0 0 1 1 1 1 IA0S 0 0 1 1 0 0 1 1 TLIS 0 1 0 1 0 1 0 1 Reset WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset Ext Ext Ext Ext Reset Reset Reset Reset Enabled Sources INTA0 SW TRAP SW TRAP Ext Pin Ext Pin Timer Timer Ext Pin Ext Pin Top Level SW TRAP Ext Pin SW TRAP Ext Pin Timer Ext Pin Timer Ext Pin Operating Mode Watchdog Watchdog Watchdog Watchdog Timer Timer Timer Timer
Legend: WDG = Watchdog function SW TRAP = Software Trap Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0 interrupts), only the INTA0 interrupt is taken into account.
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) 7.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional control bits are mapped in the following registers on Page 0: Watchdog Mode Enable, (WCR.6) Top Level Interrupt Selection, (EIVR.2) Interrupt A0 Channel Selection, (EIVR.1) Note: The registers containing these bits also contain other functions. Only the bits relevant to the operation of the Timer/Watchdog are shown here. Counter Register This 16-bit register (WDTLR, WDTHR) is used to load the 16-bit counter value. The registers can be read or written "on the fly". TIMER/WATCHDOG HIGH REGISTER (WDTHR) R248 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)
7 R15 R14 R13 R12 R11 R10 R9 0 R8
TIMER/WATCHDOG PRESCALER REGISTER (WDTPR) R250 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)
7 PR7 PR6 PR5 PR4 PR3 PR2 PR1 0 PR0
Bits 7:0 = PR[7:0] Prescaler value. A programmable value from 1 (00h) to 256 (FFh).
Warning: In order to prevent incorrect operation of the Timer/Watchdog, the prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be initialised before starting the Timer/Watchdog. If this is not done, counting will start with the reset (un-initialised) values.
WATCHDOG TIMER CONTROL REGISTER (WDTCR) R251- Read/Write Register Page: 0 Reset value: 0001 0010 (12h)
7
ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT
0
OUTEN
Bits 7:0 = R[15:8] Counter Most Significant Bits.
Bit 7 = ST_SP: Start/Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting (see Warning above) Bit 6 = S_C: Single/Continuous. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bits 5:4 = INMD[1:2]: Input mode selection bits. These bits select the input mode:
INMD1 0 0 1 1 INMD2 0 1 0 1 INPUT MODE Event Counter Gated Input (Reset value) Triggerable Input Retriggerable Input
TIMER/WATCHDOG LOW REGISTER (WDTLR) R249 - Read/Write Register Page: 0 Reset value: 1111 1111b (FFh)
7 R7 R6 R5 R4 R3 R2 R1 0 R0
Bits 7:0 = R[7:0] Counter Least Significant Bits.
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ST92141 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont'd) Bit 3 = INEN: Input Enable. This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: The output is toggled at every End of Count 1: The value of the WROUT bit is transferred to the output pin on every End Of Count if OUTEN=1. Bit 1 = WROUT: Write Out. The status of this bit is transferred to the Output pin when OUTMD is set; it is user definable to allow PWM output (on Reset WROUT is set). Bit 0 = OUTEN: Output Enable bit. This bit is set and cleared by software. 0: Disable output 1: Enable output Note: This bit is ignored if the Hardware Watchdog option is enabled by pin HW0SW1 (if available). EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h)
7 x x x x x TLIS IA0S 0 x
Bit 2 = TLIS: Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source Bit 1 = IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Warning: To avoid spurious interrupt requests, the IA0S bit should be accessed only when the interrupt logic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on channel A0 before enabling this interrupt channel. A delay instruction (e.g. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the IA0S write instruction. Other bits are described in the Interrupt section.
WAIT CONTROL REGISTER (WCR) R252 - Read/Write Register Page: 0 Reset value: 0111 1111 (7Fh)
7 x WDGEN x x x x x 0 x
Bit 6 = WDGEN: Watchdog Enable (active low). Resetting this bit via software enters the Watchdog mode. Once reset, it cannot be set anymore by the user program. At System Reset, the Watchdog mode is disabled.
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ST92141 - STANDARD TIMER (STIM)
7.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic description of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals described may not be connected to external pins. For the list of STIM pins present on the particular ST9 device, refer to the pinout description in the first section of the data sheet. 7.2.1 Introduction The Standard Timer includes a programmable 16bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes capability. The Standard Timer uses an input pin (STIN) and an output (STOUT) pin. These pins, when available, may be independent pins or connected as Alternate Functions of an I/O port bit. STIN can be used in one of four programmable input modes: - event counter, - gated external input mode, Figure 52. Standard Timer Block Diagram
n
- triggerable input mode, - retriggerable input mode. STOUT can be used to generate a Square Wave or Pulse Width Modulated signal. The Standard Timer is composed of a 16-bit down counter with an 8-bit prescaler. The input clock to the prescaler can be driven either by an internal clock equal to INTCLK divided by 4, or by CLOCK2 derived directly from the external oscillator, divided by device dependent prescaler value, thus providing a stable time reference independent from the PLL programming or by an external clock connected to the STIN pin. The Standard Timer End Of Count condition is able to generate an interrupt which is connected to one of the external interrupt channels. The End of Count condition is defined as the Counter Underflow, whenever 00h is reached.
INEN INMD1 INMD2 INPUT & (See Note 2) CLOCK CONTROL LOGIC INTCLK/4 CLOCK2/x OUTMD1 OUTMD2 STOUT1 OUTPUT CONTROL LOGIC EXTERNAL INTERRUPT 1 INTERRUPT CONTROL LOGIC INTS MUX STANDARD TIMER CLOCK STP 8-BIT PRESCALER STH,STL 16-BIT DOWNCOUNTER
STIN1
END OF COUNT
INTERRUPT REQUEST Note 1: Pin not present on all ST9 devices. Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the INEN bit must be held at 0.
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ST92141 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont'd) 7.2.2 Functional Description 7.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the beginning of the next instruction. Resetting this bit will stop the counter. If the counter is stopped and restarted, counting will resume from the value held at the stop condition, unless a new constant has been entered in the Standard Timer registers during the stop period. In this case, the new constant will be loaded as soon as counting is restarted. A new constant can be written in STH, STL, STP registers while the counter is running. The new value of the STH and STL registers will be loaded at the next End of Count condition, while the new value of the STP register will be loaded immediately. WARNING: In order to prevent incorrect counting of the Standard Timer, the prescaler (STP) and counter (STL, STH) registers must be initialised before the starting of the timer. If this is not done, counting will start with the reset values (STH=FFh, STL=FFh, STP=FFh). Single/Continuous Mode. The S-C bit (STC.6) selects between the Single or Continuous mode. SINGLE MODE: at the End of Count, the Standard Timer stops, reloads the constant and resets the Start/Stop bit (the user programmer can inspect the timer current status by reading this bit). Setting the Start/Stop bit will restart the counter. CONTINUOUS MODE: At the End of the Count, the counter automatically reloads the constant and restarts. It is only stopped by resetting the Start/Stop bit. The S-C bit can be written either with the timer stopped or running. It is possible to toggle the S-C bit and start the Standard Timer with the same instruction. 7.2.2.2 Standard Timer Input Modes (ST9 devices with Standard Timer Input STIN) Bits INMD2, INMD1 and INEN are used to select the input modes. The Input Enable (INEN) bit ena-
bles the input mode selected by the INMD2 and INMD1 bits. If the input is disabled (INEN="0"), the values of INMD2 and INMD1 are not taken into account. In this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by INTCLK/4 and transitions on the input pin have no effect. Event Counter Mode (INMD1 = "0", INMD2 = "0") The Standard Timer is driven by the signal applied to the input pin (STIN) which acts as an external clock. The unit works therefore as an event counter. The event is a high to low transition on STIN. Spacing between trailing edges should be at least the period of INTCLK multiplied by 8 (i.e. the maximum Standard Timer input frequency is 3 MHz with INTCLK = 24MHz). Gated Input Mode (INMD1 = "0", INMD2 = "1") The Timer uses the internal clock (INTCLK divided by 4) and starts and stops the Timer according to the state of STIN pin. When the status of the STIN is High the Standard Timer count operation proceeds, and when Low, counting is stopped. Triggerable Input Mode (INMD1 = "1", INMD2 = "0") The Standard Timer is started by: a) setting the Start-Stop bit, AND b) a High to Low (low trigger) transition on STIN. In order to stop the Standard Timer in this mode, it is only necessary to reset the Start-Stop bit. Retriggerable Input Mode (INMD1 = "1", INMD2 = "1") In this mode, when the Standard Timer is running (with internal clock), a High to Low transition on STIN causes the counting to start from the last constant loaded into the STL/STH and STP registers. When the Standard Timer is stopped (ST-SP bit equal to zero), a High to Low transition on STIN has no effect. 7.2.2.3 Time Base Generator (ST9 devices without Standard Timer Input STIN) For devices where STIN is replaced by a connection to CLOCK2, the condition (INMD1 = "0", INMD2 = "0") will allow the Standard Timer to generate a stable time base independent from the PLL programming.
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ST92141 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont'd) 7.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = "0", OUTMD2 = "0") The output is disabled and the corresponding pin is set high, in order to allow other alternate functions to use the I/O pin. Square Wave Output Mode (OUTMD1 = "0", OUTMD2 = "1") The Standard Timer toggles the state of the STOUT pin on every End Of Count condition. With INTCLK = 24MHz, this allows generation of a square wave with a period ranging from 333ns to 5.59 seconds. PWM Output Mode (OUTMD1 = "1") The value of the OUTMD2 bit is transferred to the STOUT output pin at the End Of Count. This allows the user to generate PWM signals, by modifying the status of OUTMD2 between End of Count events, based on software counters decremented on the Standard Timer interrupt. 7.2.3 Interrupt Selection The Standard Timer may generate an interrupt request at every End of Count. Bit 2 of the STC register (INTS) selects the interrupt source between the Standard Timer interrupt and the external interrupt pin. Thus the Standard Timer Interrupt uses the interrupt channel and takes the priority and vector of the external interrupt channel. If INTS is set to "1", the Standard Timer interrupt is disabled; otherwise, an interrupt request is generated at every End of Count. Note: When enabling or disabling the Standard Timer Interrupt (writing INTS in the STC register) an edge may be generated on the interrupt channel, causing an unwanted interrupt. To avoid this spurious interrupt request, the INTS bit should be accessed only when the interrupt log-
ic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. A delay instruction (i.e. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the INTS write instruction. 7.2.4 Register Mapping Depending on the ST9 device there may be up to 4 Standard Timers (refer to the block diagram in the first section of the data sheet). Each Standard Timer has 4 registers mapped into Page 11 in Group F of the Register File In the register description on the following page, register addresses refer to STIM0 only.
STD Timer Register STIM0 STH0 R240 STL0 R241 STP0 R242 STC0 R243 STIM1 STH1 R244 STL1 R245 STP1 R246 STC1 R247 STIM2 STH2 R248 STL2 R249 STP2 R250 STC2 R251 STIM3 STH3 R252 STL3 R253 STP3 R254 STC3 R255 Register Address (F0h) (F1h) (F2h) (F3h) (F4h) (F5h) (F6h) (F7h) (F8h) (F9h) (FAh) (FBh) (FCh) (FDh) (FEh) (FFh)
Note: The four standard timers are not implemented on all ST9 devices. Refer to the block diagram of the device for the number of timers.
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ST92141 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont'd) 7.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)
7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 0 ST.8
STANDARD TIMER CONTROL (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h)
7 ST-SP S-C INMD1 INMD2 INEN
REGISTER
0 INTS OUTMD1 OUTMD2
Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE REGISTER (STL) R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)
7 ST.7 ST.6 ST.5 ST.4 ST.3 ST.2 ST.1 0 ST.0
Bit 7 = ST-SP: Start-Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting Bit 6 = S-C: Single-Continuous Mode Select. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bits 5:4 = INMD[1:2]: Input Mode Selection. These bits select the Input functions as shown in Section 7.2.2.2, when enabled by INEN.
INMD1 0 0 1 1 INMD2 0 1 0 1 Mode Event Counter mode Gated input mode Triggerable mode Retriggerable mode
Bits 7:0 = ST.[7:0]: Counter Low Byte. Writing to the STH and STL registers allows the user to enter the Standard Timer constant, while reading it provides the counter's current value. Thus it is possible to read the counter on-the-fly. STANDARD TIMER PRESCALER REGISTER (STP) R242 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)
7 0
STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0
Bit 3 = INEN: Input Enable. This bit is set and cleared by software. If neither the STIN pin nor the CLOCK2 line are present, INEN must be 0. 0: Input section disabled 1: Input section enabled Bit 2 = INTS: Interrupt Selection. 0: Standard Timer interrupt enabled 1: Standard Timer interrupt is disabled and the external interrupt pin is enabled. Bits 1:0 = OUTMD[1:2]: Output Mode Selection. These bits select the output functions as described in Section 7.2.2.4.
OUTMD1 0 0 1 OUTMD2 0 1 x Mode No output mode Square wave output mode PWM output mode
Bits 7:0 = STP.[7:0]: Prescaler. The Prescaler value for the Standard Timer is programmed into this register. When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
7.3 EXTENDED FUNCTION TIMER (EFT) 7.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the INTCLK prescaler. 7.3.2 Main Features s Programmable prescaler: INTCLK divided by 2, 4 or 8. s Overflow status flag and maskable interrupts s External clock input (must be at least 4 times slower than the INTCLK clock speed) with the choice of active edge s Output compare functions with - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse width modulation mode (PWM) s One pulse mode s 5 alternate functions on I/O ports* s Up to 3 separate Timer interrupts or a global interrupt (depending on device) mapped on external interrupt channels: - ICI: Timer Input capture interrupt. - OCI: Timer Output compare interrupt. - TOI: Timer Overflow interrupt. - EFTI: Timer Global interrupt (replaces ICI, OCI and TOI). The Block Diagram is shown in Figure 53. Table 21. EFT Pin Naming conventions
Function Input Capture 1 ICAP1 Input Capture 2 ICAP2 Output Compare 1 OCMP1 Output Compare 2 OCMP2 EFT0 ICAPA0 ICAPB0 EFT1 ICAPA1 ICAPB1 EFTn ICAPAn ICAPBn
OCMPA0 OCMPA1 OCMPAn OCMPB0 OCMPB1 OCMPBn
*Note 1: Some external pins are not available on all devices. Refer to the device pin out description. *Note 2: Refer to the device interrupt description, to see if a single timer interrupt is used, or three separate interrupts. 7.3.3 Functional Description 7.3.3.1 Counter The principal block of the Programmable Timer is a 16-bit free running counter and its associated 16-bit registers: Counter Registers - Counter High Register (CHR) is the most significant byte (MSB). - Counter Low Register (CLR) is the least significant byte (LSB). Alternate Counter Registers - Alternate Counter High Register (ACHR) is the most significant byte (MSB). - Alternate Counter Low Register (ACLR) is the least significant byte (LSB). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (overflow flag), (see note page 98). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 22 Clock Control Bits. The value in the counter register repeats every 131.072, 262.144 or 524.288 INTCLK cycles depending on the CC1 and CC0 bits.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Figure 53. Timer Block Diagram ST9 INTERNAL BUS
INTCLK
MCU-PERIPHERAL INTERFACE
8 high
8 low high high high high low low low low
2
16 16
8-bit buffer EXEDG
8
8
8
8
8
8
8
8
16
1/2 1/4 1/8 16 BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER OUTPUT COMPARE REGISTER OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER INPUT CAPTURE REGISTER
1
1
CC1 CC0
16
TIMER INTERNAL BUS
16 16
EXTCLK
OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1 EDGE DETECT CIRCUIT2
ICAP1
6
ICAP2
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0 0 0
OCMP1
SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM
LATCH2
OCMP2
CC1
CC0 IEDG2 EXEDG
CR1
ETOI EOC EICI
CR2
0 0 0 0 TOIS OCIS ICIS EFTIS
EEFTI 10 10 10 10
CR3
EFTI
TOI
OCI
ICI
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MSB Other instructions
Returns the buffered
LSB is buffered
At t0 +Dt Read LSB
LSB value at t0
Sequence completed
The user must read the MSB first, then the LSB value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read. An overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set - TOIS bit of the CR3 register is set (or EFTIS bit if only global interrupt is available). If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done by: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. This feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the reset count (MCU awakened by a Reset). 7.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of INTCLK. At least four falling edges of the INTCLK must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the INTCLK frequency.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Figure 54. Counter Timing Diagram, INTCLK divided by 2
INTCLK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF FFFD FFFE FFFF 0000 0001 0002 0003
Figure 55. Counter Timing Diagram, INTCLK divided by 4
INTCLK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF FFFC FFFD 0000 0001
Figure 56. Counter Timing Diagram, INTCLK divided by 8
INTCLK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
OVERFLOW FLAG TOF
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9
ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.3.3 Input Capture In this section, the index, i, may be 1 or 2. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition detected by the ICAPi pin (see figure 5).
MS Byte ICiR ICiHR LS Byte ICiLR
ICi Rregister is a read-only register. The active transition is software programmable through the IEDGi bit of the Control Register (CRi). Timing resolution is one count of the free running counter: (INTCLK/CC[1:0]). Procedure To use the input capture function select the following in the CR2 register: - Select the timer clock (CC[1:0] (see Table 22 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit. And select the following in the CR1 register:
- Set the ICIE bit to generate an interrupt after an input capture. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit. When an input capture occurs: - ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 58). - A timer interrupt is generated if the ICIE bit is set and the ICIS bit (or EFTIS bit if only global interrupt is available) is set. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request is done by: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Note: After reading the ICiHR register, transfer of input capture data is inhibited until the ICiLR register is also read. The ICiR register always contains the free running counter value which corresponds to the most recent input capture.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Figure 57. Input Capture Block Diagram
ICAP1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
ICAP2
(Status Register) SR IC2R IC1R
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 58. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.3.4 Output Compare In this section, the index, i, may be 1 or 2. This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the free running counter each timer clock cycle.
MS Byte OCiR OCiHR LS Byte OCiLR
- A timer interrupt is generated if the OCIE bit is set in the CR2 register and OCIS bit (or EFTIS bit if only global interrupt is available) is set in the CR3 register. Clearing the output compare interrupt request is done by: 3. Reading the SR register while the OCFi bit is set. 4. An access (read or write) to the OCiLR register. Note: After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when match is found but an interrupt could be generated if the OCIE bit is set. The value in the 16-bit OCiR register and the OLVLi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. The OCiR register value required for a specific timing application can be calculated using the following formula:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (INTCLK/CC[1:0]). Procedure To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i function. - Select the timer clock CC[1:0] (see Table 22 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE and OCIS bits (or EFTIS bit if only global interrupt is available) to generate an interrupt if it is needed. When match is found: - OCFi bit is set. - The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset and stays low until valid compares change it to OLVLi level).
OCiR =
Where:
t * INTCLK
(CC1.CC0)
= Desired output compare period (in seconds) INTCLK = Internal clock frequency CC1-CC0 = Timer clock prescaler The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
t
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Figure 59. Output Compare Block Diagram
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
(Control Register 2) CR2 (Control Register 1) CR1
OUTPUT COMPARE CIRCUIT
OCIE
OLVL2
OLVL1
Latch 1
OCMP1
Latch 2
OCMP2
16-bit
16-bit
OC1R
OC2R
OCF1
OCF2
0
0
0
(Status Register) SR
Figure 60. Output Compare Timing Diagram, Internal Clock Divided by 2
INTCLK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OCFi AND OCMPi PIN (OLVLi=1) FFFC FFFD FFFD FFFE FFFF 0000
CPU writes FFFF
FFFF
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.3.5 Forced Compare Mode In this section i may represent 1 or 2. The following bits of the CR1 register are used:
FOLV2 FOLV1 OLVL2 OLVL1
Load the OC1R register with the value corresponding to the length of the pulse (see the formula in Section 7.3.3.7).
One pulse mode cycle
When event occurs on ICAP1 Counter is initialized to FFFCh
When the FOLVi bit is set, the OLVLi bit is copied to the OCMPi pin. The OLVLi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is not set, and thus no interrupt request is generated. 7.3.3.6 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use one pulse mode, select the following in the the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit. And select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 22 Clock Control Bits). Figure 61. One Pulse Mode Timing
OCMP1 = OLVL2 When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin. When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 61). Note: The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
COUNTER ICAP1 OCMP1
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.3.7 Pulse Width Modulation Mode Pulse Width Modulation mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode uses the complete Output Compare 1 function plus the OC2R register. Procedure To use pulse width modulation mode select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. And select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock CC[1:0] bits (see Table 22 Clock Control Bits). Load the OC2R register with the value corresponding to the period of the signal. Load the OC1R register with the value corresponding to the length of the pulse if (OLVL1=0 and OLVL2=1). If OLVL1=1 and OLVL2=0 the length of the pulse is the difference between the OC2R and OC1R registers. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
Where: - t = Desired output compare period (seconds) - INTCLK = Internal clock frequency - CC1-CC0 = Timer clock prescaler The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 62).
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh
Note: After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. The Input Capture interrupts are available. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
t * INTCLK - 5
CC[1:0]
Figure 62. Pulse Width Modulation Mode Timing
34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC
COUNTER OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.4 Interrupt Management The interrupts of the Extended Function Timer are mapped on the eight external interrupt channels of the microcontroller (refer to the "Interrupts" chapter). Depending on device specification, one of the following configurations can occur: - The three interrupt sources are mapped on three different interrupt channels (to use this feature, the EFTIS bit must be reset) - The three interrupt sources are mapped on the same interrupt channel (to use this feature, the EFTIS bit must be set) Each External Interrupt Channel has: - A trigger control bit in the EITR register (R242 Page 0) - A pending bit in the EIPR register (R243 Page 0) - A mask bit in the EIMR register (R244 - Page 0) Program the interrupt priority level using the EIPLR register (R245 - Page 0). For a description of these registers refer to the "Interrupts" and "DMA" chapters. Use of three interrupt channels To use the interrupt features, for each interrupt channel used, perform the following sequence: - Set the priority level of the interrupt channel(s) used for the Extended Function Timer (EIPRL register) - Select the interrupt trigger edge(s) as rising edge (set the corresponding bit(s) in the EITR register) - Set the OCIS and/or ICIS and/or TOIS bit(s) of the CR3 register to select the peripheral interrupt source(s) - Set the OCIE and/or ICIE and/or TOIE bit(s) of the CR1 register to enable the peripheral to perform interrupt requests on the desiderate events - In the EIPR register, reset the pending bit(s) of the interrupt channels used by the peripheral interrupts to avoid any spurious interrupt requests being performed when the mask bit(s) is/are set - Set the mask bit(s) of the interrupt channel(s) used to enable the MCU to acknowledge the interrupt requests of the peripheral.
Use of one external interrupt channel for all the interrupts To use the interrupt features, perform the following sequence: - Set the priority level of the interrupt channel used (EIPRL register) - Select the interrupt trigger edge as rising edge (set the corresponding bit in the EITR register) - Set the EFTIS bit of the CR3 register to select the peripheral interrupt sources - Set the OCIE and/or ICIE and/or TOIE bit(s) of the CR1 register to enable the peripheral to perform interrupt requests on the wanted events - In the EIPR register, reset the pending bit of the interrupt channel used by the peripheral interrupts to avoid any spurious interrupt requests being performed when the mask bits is set - Set the mask bits of the interrupt channels used to enable the MCU to acknowledge the interrupt requests of the peripheral. Caution: Care should be taken when using only one of the input capture pins, as both capture interrupts are enabled by the ICIE bit in the CR1 register. If only ICAP1 is used (for example), an interrupt can still be generated by the ICAP2 pin when this pin toggles, even if it is configured as a standard output. If this case, the interrupt capture status bits in the SR register should handled in polling mode. Caution: 1. It is mandatory to clear all EFT interrupt flags simultaneously at least once before exiting an EFT timer interrupt routine (the SR register must = 00h at some point during the interrupt routine), otherwise no interrupts can be issued on that channel anymore. Refer to the following assembly code for an interrupt sequence example. 2. Since a loop statement is needed inside the IT routine, the user must avoid situations where an interrupt event period is narrower than the duration of the interrupt treatment. Otherwise nested interrupt mode must be used to serve higher priority requests.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Note: A single access (read/write) to the SR regisregisters must be accessed if the corresponding ter at the beginning of the interrupt routine is the flag is set. It is not necessary to access the SR first step needed to clear all the EFT interrupt register between these instructions, but it can flags. In a second step, the lower bytes of the data done. ; INTERRUPT ROUTINE EXAMPLE push R234 ; Save current page spp #28 ; Set EFT page L6: cp R254,#0 ; while E0_SR is not cleared jxz L7 tm R254,#128 ; Check Input Capture 1 flag jxz L2 ; else go to next test ld r1,R241 ; Dummy read to clear IC1LR ; Insert your code here L2: tm R254,#16 ; Check Input Capture 2 flag jxz L3 ; else go to next test ld r1,R243 ; Dummy read to clear IC2LR ; Insert your code here L3: tm R254,#64 ; Check Input Compare 1 flag jxz L4 ; else go to next test ld r1,R249 ; Dummy read to clear OC1LR ; Insert your code here L4: tm R254,#8 ; Check Input Compare 2 flag jxz L5 ; else go to next test ld r1,R251 ; Dummy read to clear OC1LR ; Insert your code here L5: tm R254,#32 ; Check Input Overflow flag jxz L6 ; else go to next test ld r1,R245 ; Dummy read to clear Overflow flag ; Insert your code here jx L6 L7: pop R234 ; Restore current page iret
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) 7.3.5 Register Description Each Timer is associated with three control and one status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Notes: 1. In the register description on the following pages, register and page numbers are given using the example of Timer 0. On devices with more than one timer, refer to the device register map for the adresses and page numbers. 2. To work correctly with register pairs, it is strongly recommended to use single byte instructions. Do not use word instructions to access any of the 16-bit registers. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) R240 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR) R241 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) R242 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) R243 - Read Only Register Page: 28 Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) COUNTER HIGH REGISTER (CHR) R244 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) R246 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
COUNTER LOW REGISTER (CLR) R245 - Read/Write Register Page: 28 Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) R247 - Read/Write Register Page: 28 Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 MSB 0 LSB
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) R248 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) R250 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) R249 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) R251 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) CONTROL REGISTER 1 (CR1) R252 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h)
7 0
1: Forces the OLVL2 bit to be copied to the OCMP2 pin. Bit 3 = FOLV1 Forced Output Compare 1. 0: No effect. 1: Forces OLVL1 to be copied to the OCMP1 pin. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OC2E is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. 0: No effect.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) CONTROL REGISTER 2 (CR2) R253 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h)
7 0
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The value of the timer clock depends on these bits: Table 22. Clock Control Bits
CC1 0 0 1 1 CC0 0 1 0 1 Timer Clock
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 function is enabled, but the OCMP1 pin is a general I/O. 1: Output Compare 1 function is enabled, the OCMP1 pin is dedicated to the Output Compare 1 capability of the timer. Bit 6 = OC2E Output Compare 2 Enable. 0: Output Compare 2 function is enabled, but the OCMP2 pin is a general I/O. 1: Output Compare 2 function is enabled, the OCMP2 pin is dedicated to the Output Compare 2 capability of the timer. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
INTCLK / 4 INTCLK / 2 INTCLK / 8
External Clock (where available)
Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the free running counter. 0: A falling edge triggers the free running counter. 1: A rising edge triggers the free running counter.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) STATUS REGISTER (SR) R254 - Read Only Register Page: 28 Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
CONTROL REGISTER 3 (CR3) R255 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h)
7 0 0 0 0 TOIS OCIS ICIS 0 EFTIS
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
Bit 7-4 = Unused Read as 0. Bit 3 = TOIS Timer Overflow Interrupt Selection. 0: Select External interrupt. 1: Select Timer Overflow Interrupt. Bit 2 = OCIS Output Compare Interrupt Selection. 0: Select External interrupt. 1: Select Timer Output Compare Interrupt. Bit 1 = ICIS Input Capture Interrupt Selection. 0: Select External interrupt. 1: Select Timer Input Capture Interrupt. Bit 0 = EFTIS Global Timer Interrupt Selection. 0: Select External interrupt. 1: Select Global Timer Interrupt.
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Table 23. Extended Function Timer Register Map
Address (Dec.) R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 Register Name IC1HR Reset Value IC1LR Reset Value IC2HR Reset Value IC2LR Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value OC1HR Reset Value OC1LR Reset Value OC2HR Reset Value OC2LR Reset Value CR1 Reset Value CR2 Reset Value SR Reset Value CR3 Reset Value 7 MSB x MSB x MSB x MSB x MSB 1 MSB 1 MSB 1 MSB 1 MSB 1 MSB 0 MSB 1 MSB 0 OC1E 0 ICIE 0 ICF1 0 0 0 0 OC2E 0 OCIE 0 OCF1 0 0 0 0 OPM 0 TOIE 0 TOF 0 0 0 0 PWM 0 FOLV2 0 ICF2 0 0 0 0 CC1 0 FOLV1 0 OCF2 0 TOIS 0 0 CC0 0 OLVL2 0 0 0 OCIS 0 0 IEDG2 0 IEDG1 0 0 0 ICIS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x 6 5 4 3 2 1 0 LSB x LSB x LSB x LSB x LSB 1 LSB 0 LSB 1 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 EXEDG 0 OLVL1 0 0 0 EFTIS 0
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ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont'd) Table 24. Extended Function Timer Page Map
Timer number EFT0 Page (hex) 1C
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
7.4 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) 7.4.1 Introduction The IMC controller is designed for variable speed motor control applications. Three PWM outputs are available for controlling a three-phase motor drive. Rotor speed feedback is provided by capturing a tachogenerator input signal. 7.4.2 Main Features s 10-bit PWM Up/Down Counter s Classical and zerocentered PWM operating modes s Full-scale PWM generation s 6-bit dead time generator s Rotor speed measurement s 8 interrupt sources + 1 NMI Figure 63. IMC Controller Block Diagram
NMIE bit NMI NMIL bit Tacho Prescaler Reg. 12-Bit Prescaler 8-Bit Tacho Compare Reg.
OVF
7.4.3 Functional Description The IMC controller consists of the following function blocks: - Input and Output pins - Rotor speed measurement - 3-Phase PWM signal generation - 6-bit Dead Time generation - Polarity selection - Interrupt generation The block diagram is shown in Figure 63.
OTC Int.
NMI Control Logic NMI Int.
16-Bit Tacho Counter
CLR on CPT
CPT Int. TACHO 16-Bit Tacho Capture Reg. 10-bit Preload Compare 0 Reg. 10-bit Compare 0 Reg. PWM Counter Prescaler Reg. INTCLK 8-bit Prescaler DIV 2 ZPC Int. CPT=0 11-bit Compare U Reg. 11-bit Preload Compare U Reg. CPU Int. 10-bit PWM Counter CMS bit CPC bit Dead Time Generator Reg. Dead Time Generator UH UL CM0 Int.
ADT Int. CPT=0 8-bit Repetition ZPC Int. Down-Counter
CPV Int. 11-bit Compare V Reg. 11-bit Preload Compare V Reg.
Dead Time Generator
Polarity Selection & Output Registers
VH VL
11-bit Compare W Reg. 8-Bit Repetition Counter Reg. 11-bit Preload Compare W Reg.
CPW Int.
Dead Time Generator
WH WL
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) 7.4.3.1 Input and Output pins - Input Pin TACHO: Signal input from a tachogenerator for measuring the rotor speed. NMI: Input signal for disabling the IMC output and sending an interrupt request to the ST9 core. - Output Pins UH, UL, VH, VL, WH, WL: 3-Phase PWM signals and complementary signals (dedicated pins, refer to device Pin Description). Note: The INTCLK signal is the internal clock of the ST9 microcontroller (system clock). 7.4.3.2 Rotor Speed Measurement The TACHO signal is input from a Schmitt trigger port. When a rising and/or falling edge occurs (programmable edge sensitivity), the IMC controller does the following: - Captures the 16-bit Tacho Counter - Clears the Tacho Counter (if CCPT bit is set) - Generates a CPT interrupt The 16-bit Tacho Counter clock is derived from the clock used by the PWM Counter, through a 12-bit prescaler. The 12-bit prescaler divides by 1, 2, 3, ......, 4096. If no edge occurs on the TACHO signal or the event sensitivity is disabled (see Table 25) and the 16-bit counter is running, an OTC overflow interrupt will be issued when the MSB (Most Significant Byte) of the Tacho Counter reaches the Tacho Compare register value.
7.4.3.3 Three-Phase PWM Generator The 3-Phase PWM signal is generated using a 10bit PWM Counter and three 11-bit Compare registers one for each phase (U, V, W). The 10-bit PWM Counter clock is supplied through a 8-bit prescaler (dividing by 1, 2, 3, .., 256). It can work in Zerocentered mode or in Classical mode. The mode is selected by the CMS bit in the PCR0 register: Zerocentered Mode In this operating mode, the PWM Counter counts up to the value loaded in the 10-bit Compare 0 register then counts down until it reaches zero and restarts counting up. Classical Mode In this operating mode, the PWM Counter counts up to the value loaded in the 10-bit Compare Register. Then the PWM Counter is cleared and it restarts counting up. Figure 64 shows the counting sequence in Classical and Zerocentered mode. PWM signal generation in Zerocentered mode In this mode, all three PWM signals are set to `0' when the PWM Counter reaches, in up-counting, the corresponding 11-bit Compare register value and they are set to `1' when the PWM Counter reaches the 11-bit Compare value again in downcounting. The comparison is performed between the PWM Counter value extended to 11 bits and the 11-bit Compare register (either in Zerocentered or in Classical mode).
Figure 64. Counting sequence in Zerocentered and Classical mode
Zerocentered mode
0
1
2
....
15
16
15
....
2
1
0
1
T
Classical mode
0
1
2
.....
15
16
0
1
.....
16
0
1
T T = PWM period, Value of 10-bit Compare Register= 16
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) If the 11-bit Compare register value is greater than the extended Compare 0 Register (the 11th bit is set to `0'), the corresponding PWM output signal is held at `1'.
If the 11-bit Compare register value is 0, the corresponding PWM output signal is held at `0'. Figure 65 shows some Zerocentered PWM waveforms in an example where the Compare 0 register value = 8.
Figure 65. Zerocentered PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
1
1
2
3
`1'
4
`0' 1 Compare Register value = 4 2 Compare Register value = 7 3 Compare Register value > = 8 4 Compare Register value = 0
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) PWM signals generation in Classical mode In this mode, each of the three PWM signals set to `0' when the PWM Counter reaches, in up-counting, the corresponding 11-bit Compare register value and they are set to `1' when the PWM Counter is cleared. If the 11-bit Compare register value is greater than the extended Compare 0 register (the 11th bit is
set to `0'), the corresponding PWM output signal is held at `1'. If the 11-bit Compare register value = 0, the corresponding PWM output signal is held at `0'. Figure 66 shows some Classical PWM waves in an example where the Compare 0 register value = 8.
Figure 66. Classical PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
0
1
1
2
3
`1'
4
`0' 1 Compare Register value = 4 2 Compare Register value = 8 3 Compare Register value > 8 4 Compare Register value = 0
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) Repetition Down-Counter Both in Zerocentered and Classical working mode, the four Compare registers (one Compare 0 and three for the U, V and W phases) are updated when the PWM counter value is zero and the 8-bit Repetition Down-Counter has reached zero value by counting or by software programming (see PCR2 register). This means that data transits from the Preload Compare registers to the Compare registers every N cycles of the PWM Counter, where N is the value of the 8-bit Repetition register (N=1, 2, .., 256). 7.4.3.4 Dead Time Generator For each phase there is one 6-bit Dead Time generator. It generates two output signals: h and l. The h output signal is the same as the input phase signal except for the rising edge, which is delayed relatively to the input signal rising edge. Figure 67. Dead Time waveforms
The l output signal is the opposite of the input phase signal except the rising edge which is delayed relatively to the input signal falling edge. The delay is the same for each phase (U, V, W) and its value is: delay = T x N where T is the period of the Dead Time Generator input clock (INTCLK divided by 2) and N is the 6bit number in the Dead Time register. If the DTE bit in PCR0 register is reset, the Dead Time Generator is disabled. This means that no delays are added to the l complemented outputs. Figure 67 shows an example waveform of the U phase. If the delay is greater than the width of the active phase (l or h) then the corresponding pulse is not generated. See Figure 68 and Figure 69.
U
5V 0V
Uh
5V 0V Delay 5V
Ul Delay
0V
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) Figure 68. Dead Time waveforms with delay greater than the negative PWM pulse
U
5V 0V
Uh Delay
5V 0V
5V Ul 0V
Figure 69. Dead Time waveforms with delay greater than the positive PWM pulse
U
5V 0V
Uh
5V 0V
5V Ul Delay 0V
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) 7.4.3.5 Polarity Selection The Polarity Selection performs a logical complement of the input signals (Uh, Ul, Vh, Vl, Wh, Wl) as programmed in the Polarity Selection register. 7.4.3.6 Interrupts The IMC controller generates 8 interrupt requests and 1 NMI. Each interrupt request has a separate vector address. The NMI interrupt is managed by the ST9 as a Top Level Interrupt.The interrupt priority is fixed by hardware as listed below:
Priority Interrupt Source CPU Top Level NMI: Event on external pin Int. priority ADT: Data transfer (when data is trans0 High Priority ferred from the preload registers to the compare registers) 1 ZPC: PWM Counter Zero Event 2 CM0: PWM Counter Compare 0 Event 3 CPT: Tacho Counter Capture Event CPU: Compare U Event (PWM counter 4 reached U compare value) CPV: Compare V Event (PWM counter 5 reached V compare value) CPW: Compare W Event (PWM coun6 ter reached W compare value) 7 Low Priority OTC: Tacho Counter Overflow
7.4.4 Tacho Counter Operating mode The Tacho Counter can work in One Shot mode or in Continuous mode. In both Continuous or One Shot mode the Capture event can be generated by hardware (TACHO Pin) or by software (STC bit in the PCR1 register) according to the value of the TES bit in the PCR1 register. When the CTC bit in the PCR0 register is set, the TACHO Counter is cleared (this bit is reset by hardware). 7.4.4.1 Tacho Counter in One Shot mode In this operating mode (TCB bit = 1 in the PCR1 register) the Counter does the following: - Counting is started by setting the TCE bit in the PCR0 register. - When a Capture event occurs, counting is stopped (TCE bit is cleared), the value is captured and a CPT interrupt is generated (if the
CCPT bit in the PCR1 register is set, the Counter is cleared). - When the MSB of Tacho Counter reaches the Tacho Compare register value, the Counter is stopped (TCE bit is cleared) and the OTC interrupt is generated. 7.4.4.2 Tacho Counter in Continuous mode In this operating mode (TCB bit = 0 in the PCR1 register) the Counter does the following: - Counting is started by setting the TCE bit in the PCR0 register. - Every Capture event, the value is captured and a CPT interrupt is generated (if the CCPT bit in the PCR1 register is set, the Counter is cleared). - When the MSB of Tacho Counter reaches the Tacho Compare register value, an OTC interrupt is generated. 7.4.5 IMC Operating mode The IMC controller can work in two different modes: - Hardware Operating mode (DTS bit = 0 in PRCR2 register) - Software Operating mode (DTS bit = 1 in PRCR2 register) In both modes, when the corresponding event occurs, the ADT and the other interrupts are generated. When the CPC bit in the PCR0 register is set, the PWM Counter is cleared (this bit is reset by software). 7.4.5.1 IMC Hardware Operating mode After system reset, the Compare U, V, W and Compare 0 register values are all "0". When the PWM Counter is enabled (by setting the PCE bit in the PCR0 register) and every time the Repetition Counter and the PWM Counter reach "0" value, the Repetition Counter is loaded, the preload registers are loaded into the Compare registers and an ADT interrupt is generated. Note: If an ADT (or any other interrupt) is generated and the previous one is not completed, the last one will be lost without any error condition being issued.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) 7.4.5.2 IMC Software Operating mode In this operating mode, the Repetition register and any Compare register can be independently updated by software by setting the SDT bit in the PCR2 register (this bit will be reset by hardware) and the corresponding enable bit in the same register. No hardware loading is performed when an ADT interrupt is generated. Note: The Repetition Counter is decremented immediately when the Repetition Counter is updated. Figure 70. IMC Output selection.
7.4.6 IMC Output selection The IMC Output can be selected from the following sources: - OPR register (bit 5:0), by setting the ODS bit in the OPR register. - Dead Time Generator outputs, by setting the ODCS bit in PCR0 register. - PWM Counter outputs (h and l) are not complemented when the ODCS bit is reset. Figure 70 shows the IMC output selection.
OPR Register Polarity Selection ODS bit UH UL VH VL WH WL ODCS bit
1
Dead Time Generator PWM Counter
1 0 0
PSR Register
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) 7.4.7 NMI management Figure 71 shows how the external input NMI signal is managed by the IMC peripheral. After an ST9 reset, the NMIE bit in the PCR1 register is cleared, which means that NMI signal coming from the external pin is sent, as is, to the ST9 core without affecting the IMC peripheral. If the NMIE bit is set, when an NMI event occurs on the external pin, it will be acknowledged (depending on the value of the NMIL bit in the PSR register). In this case: - The NMI bit in the IMCIVR register is set - The dedicated output pins of the IMC are put in high impedance - A high level signal is sent to the ST9 Top Level interrupt - The OPE bit is cleared (as the NMI interrupt signal is no longer active) Figure 71. NMI management by the IMC peripheral
NMI to ST9 core 1 0 NMIE bit
Notes: 1. Because the signal to the ST9 top level interrupt is active high, the TLTEV bit in the EIVR register must be set. 2. When the user wants to leave the NMI interrupt routine, it is strongly recommended to verify, before leaving the routine, that the NMI pending bit (bit 3 of IMCIVR) is really at "0". To do this, the user can try to write the NMI pending bit to "0" repeatedly until it has successfully been cleared. The NMI pending bit in IMCIVR register can be written to "0" only if the external NMI signal is no longer active. This makes sure that no NMI event will be lost. If the user leaves the NMI interrupt routine without clearing the NMI pending bit, no other NMI interrupt can be issued afterwards because the ST9 top level interrupt is edge sensitive.
NMI bit
NMI from EXT pin
Level selection
NMIL bit
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) 7.4.8 Register Description TACHO CAPTURE REGISTER HIGH (TCPTH) R240 - Read Only Register Page: 51 Reset Value: undefined
7 0
TACHO COMPARE REGISTER (TCMP) R242 - Read/Write Register Page: 51 Reset Value: 1111 1111 (FFh)
7 0
TCM7 TCM6 TCM5 TCM4 TCM3 TCM2 TCM1 TCM0 TCH7 TCH6 TCH5 TCH4 TCH3 TCH2 TCH1 TCH0
Bit 7:0 = TCH[7:0] Most Significant Byte of Tacho Capture register. TACHO CAPTURE REGISTER LOW (TCPTL) R241 - Read Only Register Page: 51 Reset Value: undefined
7 0
Bit 7:0 = TCM[7:0] Byte of Tacho Compare register. When the Most Significant Byte of the Tacho Counter reaches TCMP value, the Tacho Counter is cleared and an OTC interrupt is generated both in Continuous and One Shot mode.
TCL7 TCL6 TCL5 TCL4 TCL3 TCL2 TCL1 TCL0
Bit 7:0 = TCL[7:0] Low Byte of Tacho Capture register.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) INTERRUPT PENDING REGISTER (IPR) R243 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
CM0 CPT OTC ADT ZPC CPU CPV
0
CPW
hardware when the PWM Counter reaches the Compare U register value while CPUE=1. In Zerocentered Mode (CMS bit =1), this bit is set by hardware when the PWM Counter reaches the Compare U register value while CPUE=1 in up or downcounting (depending on the UDIS bit in the PSR register). The CPU bit must be cleared by software. 0: No CPU interrupt occurred 1: CPU interrupt pending Bit 1 = CPV: Compare V pending bit. In Classical Mode (CMS bit = 0), this bit is set by hardware when the PWM Counter reaches the Compare V register value while CPVE=1. In Zerocentered Mode (CMS bit =1), this bit is set by hardware when the PWM Counter reaches the Compare V register value while CPVE=1 in up or downcounting (depending on the UDIS bit in the PSR register). The CPPRS register). The CPV bit must be cleared by software. 0: No CPV interrupt occurred 1: CPV interrupt pending Bit 0 = CPW: Compare W pending bit. In Classical Mode (CMS bit = 0), this bit is set by hardware when the PWM Counter reaches the Compare W register value while CPWE=1. In Zerocentered Mode (CMS bit =1), this bit is set by hardware when the PWM Counter reaches the Compare W register value while CPWE=1 in up or downcounting (depending on the UDIS bit in the PSR register). The CPW bit must be cleared by software. 0: No CPW interrupt occurred 1: CPW interrupt pending Note 1: None of the bits in the IPR register can be set by software, they can only be cleared. Note 2: To clear the bits in the IPR register, the user must not use direct addressing bit instructions such as AND, OR, BRES, etc. because some interrupts may not be generated as expected. To avoid this, do the following: To clear one pending bit of the IPR register, load the register with the mask corresponding to the bit to be cleared. For example: To clear the CPW bit, use the instruction LD R243,#1111 1110 rather than the instruction AND R243,#1111 1110.
Bit 7 = CM0: Compare 0 of PWM pending bit. This bit is set by hardware when the PWM counter reaches the value in the Compare 0 register while CM0E=1. The CM0 bit must be cleared by software. 0: No CMP0 interrupt occurred 1: CMP0 interrupt pending Bit 6 = CPT: Capture of Tacho counter pending bit. This bit is set by hardware when a Tacho signal event occurs while CPTE=1. The CPT bit must be cleared by software. 0: No CPT interrupt occurred 1: CPT interrupt pending Bit 5 = OTC: Overflow of Tacho counter pending bit. This bit is set by hardware on a Tacho counter overflow while OTCE=1. The OTC bit must be cleared by software. 0: No OTC interrupt occurred 1: OTC interrupt pending Bit 4 = ADT: Automatic Data Transfer pending bit. This bit is set by hardware when data is transferred from the preload registers to the compare registers while ADTE=1. The ADT bit must be cleared by software. 0: No ADT interrupt occurred 1: ADT interrupt pending Bit 3 = ZPC: Zero of PWM counter pending bit. This bit is set by hardware when the PWM counter reaches zero while ZPCE=1. The ZPC bit must be cleared by software. 0: No ZPC interrupt occurred 1: ZPC interrupt pending Bit 2 = CPU: Compare U pending bit. In Classical Mode (CMS bit = 0), this bit is set by
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) TACHO PRESCALER REGISTER HIGH (TPRSH) R244 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 0 TPRH TPRH TPRH TPRH 3 2 1 0
PWM COUNTER PRESCALER (CPRS) R246 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
REGISTER
0
CPR7 CPR6 CPR5 CPR4 CPR3 CPR2 CPR1 CPR0
Bit 7:4 = Reserved. Bit 3:0 = TPRH[3:0] Most Significant Bits of tacho prescaler value (N). TACHO PRESCALER REGISTER LOW (TPRSL) R245 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
Bit 7:0 = CPR[7:0] PWM counter prescaler value (N). This value divides the INTCLK frequency by (N +1), i.e. if N = 0, INTCLK is divided by 1. REPETITION COUNTER REGISTER (REP) R247 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 0
7
0
REP7 REP6 REP5 REP4 REP3 REP2 REP1 REP0
TPRL TPRL TPRL TPRL TPRL TPRL TPRL TPRL 7 6 5 4 3 2 1 0
Bit 7:0 = REP[7:0] Repetition counter value (N). If N = 0, each time the PWM Counter reaches zero, the Compare registers are updated and an ADT interrupt is generated.
Bit 7:0 = TPRL[7:0] Low byte of tacho prescaler value (N). If N = 0 Tacho Prescaler divides by 1.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) COMPARE PHASE W PRELOAD REGISTER HIGH (CPWH) R248 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 0
COMPARE PHASE V PRELOAD REGISTER HIGH (CPVH) R250 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 0
CPWH CPWH CPWH CPWH CPWH CPWH CPWH CPWH 7 6 5 4 3 2 1 0
CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0
Bit 7:0 = CPWH[7:0] Most Significant Byte of phase W preload value COMPARE PHASE W PRELOAD REGISTER LOW (CPWL) R249 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
CPWL CPWL CPWL 7 6 5 -
Bit 7:0 = CPVH[7:0] Most Significant Byte of phase V preload value COMPARE PHASE V PRELOAD REGISTER LOW (CPVL) R251 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
CPVL7 CPVL6 CPVL5 -
0
-
0
-
Bit 7:5 = CPWL[7:5] Low bits of phase W preload value. Bit 4:0 = Reserved.
Bit 7:5 = CPVL[7:5] Low bits of phase V preload value. Bit 4:0 = Reserved.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) COMPARE PHASE U PRELOAD REGISTER HIGH (CPUH) R252 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 0
COMPARE 0 PRELOAD REGISTER (CP0H) R254 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7 -
HIGH
0 CP0H1 CP0H0
CPUH CPUH CPUH CPUH CPUH CPUH CPUH CPUH 7 6 5 4 3 2 1 0
Bit 7:0 = CPUH[7:0] Most Significant Byte of phase U preload value COMPARE PHASE U PRELOAD REGISTER LOW (CPUL) R253 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
CPUL7 CPUL6 CPUL5 -
Bit 7:2 = Reserved. Bit 1:0 = CP0H[1:0] Most Significant Bits of Compare 0 preload value. COMPARE 0 PRELOAD REGISTER (CP0L) R255 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h)
7
LOW
0
-
0
Bit 7:5 = CPUL[7:5] Low bits of phase U preload value. Bit 4:0 = Reserved.
CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0
Bit 7:0 = CP0L[7:0] Low byte of Compare 0 preload value. Note: CP0[9:0] value must be greater than 1.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) PERIPHERAL CONTROL REGISTER 0 (PCR0) R248 - Read/Write Register Page: 48 Reset Value: 1000 0011 (83h)
7
DTE TCE PCE CTC CPC CMS
PERIPHERAL CONTROL REGISTER 1 (PCR1) R249 - Read/Write Register Page: 48 Reset Value: 0000 0000 00h
7
NMIE CCPT TES STC TCB TIN1
0
UDCS ODCS
0
TIN0
Bit 7 = DTE: Dead Time Counter Enable. 0: Stop and bypass the Dead Time counter 1: Enable the Dead Time counter Bit 6 = TCE: Tacho Counter Enable. 0: Stop Tacho counter and prescaler 1: Start Tacho counter and prescaler Note: This bit is reset by the counter overflow or by the Tacho capture when the IMC controller is in one shot mode. Bit 5 = PCE: PWM Counter Enable. 0: Stop PWM Counter and prescaler 1: Start PWM Counter and prescaler Bit 4 = CTC: Clear of Tacho Counter. 0: No effect 1: Clear the Tacho Counter (this bit is reset by hardware) Bit 3 = CPC: Clear of PWM Counter. 0: No effect. 1: Clear the PWM Counter (his bit is reset by hardware) Bit 2 = CMS: PWM Counter Mode Selection. 0: Classical mode. 1: Zerocentered mode Bit 1 = UDCS: Up/Down - status (read only). This bit is set and cleared by hardware. 0: The PWM Counter is counting down. 1: The PWM Counter is counting up. Bit 0 = ODCS: Output Dead Time counter Selection 0: Select the same signal for both (h, l) outputs 1: Select complementary signal for output (Dead Time Generator outputs)
Bit 7 = Reserved. Bit 6 = NMIE: Non Maskable Interrupt Enable 0: When an NMI event occurs on the external pin, it is sent as is (independently of the NMIL value) to the ST9 core and has no effect on the IMC controller. 1: When an NMI event occurs on the external pin, if it is acknowledged (depending on the NMIL bit) an interrupt request is sent to the ST9 core (a high level signal ), the NMI pending bit (NMI bit in IMCIVR register) is set and the OPE bit is cleared. Bit 5 = CCPT: Clear on Capture of tacho counter 0: no clear on capture 1: clear on capture Bit 4 = TES: Tacho Event Selection. 0: Select capture by tacho event signal 1: Select capture by software (STC bit) Bit 3 = STC: Software tacho capture 0: No effect 1: Capture the Tacho counter (while TES=1). This bit is reset by hardware Bit 2 = TCB: Tacho Counter Mode 0: Select continuous mode. 1: Select one shot mode (counting starts when TCE bit is set and stops when a capture or an overflow event occurs). Bit 1:0 = TIN[1:0] Tacho Signal Event Sensitivity These bits select which Tacho signal event triggers the Tacho Capture register. Table 25. Tacho Signal Event Sensitivity
TIN1 0 0 1 1 TIN0 0 1 0 1 Event No operation Falling edge Rising edge Rising and falling edges
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd)) PERIPHERAL CONTROL REGISTER 2 (PCR2) R250 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h)
7
GPIE RSE CWSE CVSE CUSE C0SE SDT
POLARITY SELECTION REGISTER (PSR) R251 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h)
7
NMIL UDIS PUH PUL PVH PVL PWH
0
DTS
0
PWL
Bit 7 = GPIE: Global Peripheral Interrupt Enable. 0: Disable all IMC controller interrupts. 1: Enable all IMC controller interrupts. Bit 6 = RSE: Enable Software Data Transfer to Repetition register. 0: Disable loading of Repetition register by SDT bit 1: Enable loading of Repetition register by SDT bit Bit 5 = CWSE: Enable Software Data Transfer to Compare W. 0: Disable load of Compare W register by SDT bit 1: Enable load of Compare W register by SDT bit Bit 4 = CVSE: Enable Software Data Transfer to Compare V register. 0: Disable loading of Compare V register by SDT bit 1: Enable loading of Compare V register by SDT bit Bit 3 = CUSE: Enable Software Data Transfer to Compare U register. 0: Disable loading of Compare U register by SDT bit 1: Enable loading of Compare U register by SDT bit Bit 2 = C0SE: Enable Software Data Transfer to Compare 0 register. 0: Disable loading of Compare 0 register by SDT bit 1: Enable loading of Compare 0 register by SDT bit Bit 1 = SDT: Software Data Transfer 0: No effect 1: Transfer Data from preload to compare register (while DTS=1) (This bit is reset by hardware). Bit 0 = DTS: Data Transfer Mode Selection. 0: Hardware transfer using Repetition counter 1: Software transfer using SDT bit.
Bit 7 = NMIL: Non Maskable Interrupt Level. 0: Low level of NMI event is acknowledged. 1: High level of NMI event is acknowledged. Bit 6 = UDIS: Up-Down Interrupt Select. When the PWM Counter is working in Zerocentered Mode the meaning is: 0: The Compare interrupts (CPU, CPV, CPW) are issued when the Counter is counting up. 1: The Compare interrupts (CPU, CPV, CPW) are issued when the Counter is counting down. This bit has no effect when the Counter is working in Classical Mode Bit 5 = PUH: Polarity of Uh phase. 0: Positive logical level. 1: Complemented logical level. Bit 4 = PUL: Polarity of Ul phase. 0: Positive logical level. 1: Complemented logical level. Bit 3 = PVH: Polarity of Vh phase. 0: Positive logical level. 1: Complemented logical level. Bit 2 = PVL: Polarity of Vl phase. 0: Positive logical level. 1: Complemented logical level. Bit 1 = PWH: Polarity of Wh phase. 0: Positive logical level. 1: Complemented logical level. Bit 0: PWL: Polarity of Wl phase. 0: Positive logical level. 1: Complemented logical level.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) OUTPUT PERIPHERAL REGISTER (OPR) R252 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h)
7
OPE ODS UH UL VH VL WH
INTERRUPT MASK REGISTER (IMR) R253 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h)
7
CM0E CPTE OTCE ADTE
0
WL
0
ZPCE CPUE CPVE CPWE
Bit 7 = OPE: Output Port Enable. This bit can be set by software only if the NMI bit is cleared. 0: Output port is in high impedance (without pullup and pull-down resistor). 1: Output port is available for data transfer. Bit 6 = ODS: Output Data Selection. 0: Dead time generator data. 1: Select the Bit 5:0 data Bit 5:0 = Uh, Ul, Vh, Vl, Wh, Wl phases These bits can be sent out through the output port.
Bit 7 = CM0E: Compare 0 of PWM counter enable. 0: Disabled. 1: Enabled. Bit 6 = CPTE: Capture of Tacho counter Interrupt enable. 0: Disabled. 1: Enabled. Bit 5 = OTCE: Overflow of Tacho counter Interrupt enable. 0: Disabled. 1: Enabled. Bit 4 = ADTE: Automatic data transfer Interrupt enable. 0: Disabled. 1: Enabled. Bit 3 = ZPCE: Zero of PWM counter interrupt enable. 0: Disabled. 1: Enabled. Bit 2:0 = CPUE, CPVE, CPWE: Compare U, V, W interrupt enable. 0: Disabled. 1: Enabled.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) DEAD TIME GENERATOR REGISTER (DTG) R254 - Read/Write Register Page: 48 Reset Value: 0011 1111 (3Fh)
7 0 DTG5 DTG4 DTG3 DTG2 DTG1 DTG0
IMC INTERRUPT VECTOR REGISTER (IMCIVR) R255 - Read/Write Register Page: 48 Reset Value: undefined (17h)
7
V3 V2 V1 V0 NMI PL2 PL1
0
PL0
Bit 7:6 = Reserved. Bit 5:0 = DTG[5:0] Dead time generator value (N). The delay is N x INTCLK period multiplied by 2. If N = 0 the delay is 0.
Bit 7:4 = V[3:0]: Interrupt Vector Base Address. User programmable interrupt vector bits. The most significant nibble of the interrupt vector address is given by V[3:0]. The other nibble is given by W[3:0] where W[0] is forced to `0' and W[3:1] are set by hardware according to the Table 26 Interrupt Source Address. Table 26. Interrupt Source Address
W[3:1] 000 001 010 011 100 101 110 111 Interrupt Source ADT Data transfer ZPC Zero event of PWM counter CM0 PWM counter Compare 0 CPT Tacho capture CPU Compare U CPV Compare V CPW Compare W OTC Tacho counter overflow
Bit 3 = NMI: Non Maskable Interrupt pending bit. This bit is set by hardware when an NMI event occurs and the NMIE bit = 1. The NMI bit can be cleared by software. It cannot be set by software. As long as this bit is `1' the NMI signal to ST9 is kept active (high level). 0: No NMI pending 1: NMI pending Note: As long as the external NMI signal is active the NMI bit can not be reset. Bit 2:0 = PL[2:0]: Priority level for the peripheral interrupt.
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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont'd) Table 27. IMC Controller Register Map
Page 51 Register No. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 Page 48 Register No. R248 R249 R250 R251 R252 R253 R254 R255 Register Name TCPTH TCPTL TCMP IPR TPRSH TPRSL CPRS REP CPWH CPWL CPVH CPVL CPUH CPUL CP0H CP0L Register Name PCR0 PCR1 PCR2 PSR OPR IMR DTG IMCIVR 7 TCH7 TCL7 TCP7 CM0 TPRL7 CPR7 REP7 CPWH7 CPWL7 CPVH7 CPVL7 CPUH7 CPU7L CP0L7 7 DTE GPIE NMIL OPE CM0E V3 6 TCH6 TCL6 TCP6 CPT TPRL6 CPR6 REP6 CPWH6 CPWL6 CPVH6 CPVL6 CPUH6 CPUL6 CP0L6 6 TCE NMIE RSE UDIS ODS CPTE V2 5 TCH5 TCL5 TCP5 OTC TPRL5 CPR5 REP5 CPWH5 CPWL5 CPVH5 CPVL5 CPUH5 CPUL5 CP0L5 5 PCE CCPT CWSE PUH UH OTCE DTG5 V1 4 TCH4 TCL4 TCP4 ADT TPRL4 CPR4 REP4 CPWH4 CPVH4 CPUH4 CP0L4 4 CTC TES CVSE PUL UL ADTE DTG4 V0 3 TCH3 TCL3 TCP3 ZPC TPH3 TPRL3 CPR3 REP3 CPWH3 CPVH3 CPUH3 CP0L3 3 CPC STC CUSE PVH VH ZPCE DTG3 NMI 2 TCH2 TCL2 TCP2 CPU TPH2 TPRL2 CPR2 REP2 CPWH2 CPVH2 CPUH2 CP0L2 2 CMS TCB COSE PVL VL CPUE DTG2 PL2 1 TCH1 TCL1 TCP1 CPV TPH1 TPRL1 CPR1 REP1 CPWH1 CPVH1 CPUH1 CP0H1 CP0L1 1 UDCS TIN1 SDT PWH WH CPVE DTG1 PL1 0 TCH0 TCL0 TCP0 CPW TPH0 TPRL0 CPR0 REP0 CPWH0 CPVH0 CPUH0 CP0H0 CP0L0 0 ODCS TIN0 DTS PWL WL CPWE DTG0 PL0
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
7.5 SERIAL PERIPHERAL INTERFACE (SPI) 7.5.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another Microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 7.5.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = INTCLK/2. s Fully programmable 3-bit prescaler for a wide range of baud rates, plus a programmable divider by 2 s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 7.5.3 General Description The SPI is connected to external devices through 4 alternate pins: Figure 72. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
- MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin To use any of these alternate functions (input or output), the corresponding I/O port must be programmed as alternate function output. A basic example of interconnections between a single master and a single slave is illustrated on Figure 72. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 75) but master and slave must be programmed with the same timing mode.
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 73. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer
DR
1 0
IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL - MODF -
Ext. INT SR
-
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPOE SPIS MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
DIV2
PR
PRS2 PRS1 PRS0
ST9 PERIPHERAL CLOCK (INTCLK)
1/2
0 1
PRESCALER /1 .. /8
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4 Functional Description Figure 73 shows the serial peripheral interface (SPI) block diagram. This interface contains 4 dedicated registers: - A Control Register (CR) - A Prescaler Register (PR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, PR, SR and DR registers in Section 7.5.6for the bit definitions. 7.5.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Define the serial clock baud rate by setting/resetting the DIV2 bit of PR register, by writing a prescaler value in the PR register and programming the SPR0 & SPR1 bits in the CR register. - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 75). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPOE bits must be set (they remain set only if the SS pin is connected to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit Sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIS and SPIE bits are set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A write or a read of the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the PR register and SPR0 & SPR1 bits in the CR is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 75. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPOE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIS and SPIE bits are set. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2. A write or a read of the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 7.5.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 7.5.4.4).
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 75, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA Bit is Set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 74). CPHA Bit is Reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. This pin must be toggled high and low between each byte transmitted (see Figure 74). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 74. CPHA / SS Timing Diagram
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 75. Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Control Timing chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL Bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 76).
Figure 76. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2
nd
Step
Read DR
WCOL=0
Note: Writing in DR register instead of reading in it do not reset WCOL bit
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPOE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPOE and MSTR
bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPOE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 7.5.4.6 Overrun Condition An overrun condition occurs, when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 77). Multi-Master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one slave device during a transmission. Figure 77. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.5 Interrupt Management The interrupt of the Serial Peripheral Interface is mapped on one of the eight External Interrupt Channels of the microcontroller (refer to the "Interrupts" chapter). Each External Interrupt Channel has: - A trigger control bit in the EITR register (R242 Page 0), - A pending bit in the EIPR register (R243 Page0), - A mask bit in the EIMR register (R244 - Page 0). Program the interrupt priority level using the EIPLR register (R245 - Page 0). For a description of these registers refer to the "Interrupts" and "DMA" chapters. To use the interrupt feature, perform the following sequence: - Set the priority level of the interrupt channel used for the SPI (EIPRL register) - Select the interrupt trigger edge as rising edge (set the corresponding bit in the EITR register) - Set the SPIS bit of the CR register to select the peripheral interrupt source - Set the SPIE bit of the CR register to enable the peripheral to perform interrupt requests - In the EIPR register, reset the pending bit of the interrupt channel used by the SPI interrupt to avoid any spurious interrupt requests being performed when the mask bit is set - Set the mask bit of the interrupt channel used to enable the MCU to acknowledge the interrupt requests of the peripheral.
Note: In the interrupt routine, reset the related pending bit to avoid the interrupt request that was just acknowledged being proposed again. Then, after resetting the pending bit and before the IRET instruction, check if the SPIF and MODF interrupt flags in the SR register) are reset; otherwise jump to the beginning of the routine. If, on return from an interrupt routine, the pending bit is reset while one of the interrupt flags is set, no interrupt is performed on that channel until the flags are set. A new interrupt request is performed only when a flag is set with the other not set. 7.5.5.1 Register Map Depending on the device, one or two Serial Peripheral interfaces can be present. The previous table summarizes the position of the registers of the two peripherals in the register map of the microcontroller. Address SPI0 R240 (F0h) R241 (F1h) R242 (F2h) R243 (F3h) SPI1 R248 (F8h) R249 (F9h) R250 (FAh) R251 (FBh) Page 7 7 7 7 7 7 7 7 Name DR0 CR0 SR0 PR0 DR1 CR1 SR1 PR1
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ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.6 Register Description DATA REGISTER (SPDR) R240 - Read/Write Register Page: 7 Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Note: To use the MISO, MOSI and SCK alternate functions (input or output), the corresponding I/O port must be programmed as alternate function output. Bit 5 = SPIS Interrupt Selection. This bit is set and cleared by software. 0: Interrupt source is external interrupt 1: Interrupt source is SPI Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 7.5.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software. They select one of four baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 28. Serial Peripheral Baud Rate
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the DR register returns the value located in the buffer and not the content of the shift register (see Figure 73). CONTROL REGISTER (SPCR) R241 - Read/Write Register Page: 7 Reset Value: 0000 0000 (00h)
7 SPIE SPOE SPIS MSTR CPOL CPHA SPR1 0 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever either SPIF or MODF are set in the SR register while the other flag is 0. Bit 6 = SPOE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 7.5.4.5 Master Mode Fault). 0: SPI alternate functions disabled (MISO, MOSI and SCK can only work as input) 1: SPI alternate functions enabled (MISO, MOSI and SCK can work as input or output depending on the value of MSTR)
INTCLK Clock Divide 2 4 16 32
SPR1 0 0 1 1
SPR0 0 1 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SPSR) R242 - Read Only Register Page: 7 Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
Bits 3:0 = Unused. PRESCALER REGISTER (SPPR) R243 - Read/Write Register Page: 7 Reset Value: 0000 0000 (00h)
7 0 0 0 DIV2 0 PRS2 PRS1 PRS0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 76). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 7.5.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected
0
Bits 7:5 = Reserved, forced by hardware to 0. Bit 4 = DIV2 Divider enable. This bit is set and cleared by software. 0: Divider by 2 enabled. 1: Divider by 2 disabled. Bit 3 = Reserved. forced by hardware to 0. Bits 2:0 = PRS[2:0] Prescaler Value. These bits are set and cleared by software. The baud rate generator is driven by INTCLK/(n1*n2*n3) where n1= PRS[2:0]+1, n2 is the value of the SPR[1:0] bits, n3 = 1 if DIV2=1 and n3= 2 if DIV2=0. Refer to Figure 73. These bits have no effect in slave mode. Table 29. Prescaler Baud Rate Prescaler Division Factor 1 (no division) 2 ... 8 1 1 1 PRS2 0 0 PRS1 0 0 PRS0 0 1
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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)
7.6 ANALOG TO DIGITAL CONVERTER (ADC) Important Note: This chapter is a generic description of the ADC peripheral. However depending on the ST9 device, some or all of the interface signals described may not be connected to external pins. For the list of ADC pins present on the ST9 device, refer to the device pinout description in the first section of the data sheet. 7.6.1 Introduction The Analog to Digital Converter (ADC) comprises an input multiplex channel selector feeding a successive approximation converter. The conversion time depends on the INTCLK frequency and the prescaler factor stored in the PR[2:0] bits of the CRR register (R252). The minimum conversion time is 138 INTCLK and with the maximum prescaling factor it becomes about 16 times longer. For instance, with INTCLK at 20 MHz and PR[2:0] equal to "111", conversion of the selected channel requires 6.9s. It requires 27.45s if PR[2:0] equals "110" and so on. Refer to Table 30 for the list of conversion and sampling times. The 6.9s time includes the 4s required by the built-in Sample and Hold circuitry, which minimizes the need for external components and allows quick sampling of the signal to minimise warping and conversion error. Figure 78. Block Diagram Conversion resolution is 8 bits, with 1 LSB maximum error in the input range between VSS and the analog VDD reference. The converter uses a fully differential analog input configuration for the best noise immunity and precision performance. Two separate supply references are provided to ensure the best possible supply noise rejection. In fact, the converted digital value, is referred to the analog reference voltage which determines the full scale converted value. Naturally, Analog and Digital VSS MUST be common. If analog supplies are not present, input reference voltages are referred to the digital ground and supply. Up to 8 multiplexed Analog Inputs are available, depending on the specific device type. A group of signals can be converted sequentially by simply programming the starting address of the first analog channel to be converted and with the AUTOSCAN feature. Two Analog Watchdogs are provided, allowing continuous hardware monitoring of two input channels. An Interrupt request is generated whenever the converted value of either of these two analog inputs is outside the upper or lower programmed threshold values. The comparison result is stored in a dedicated register.
INTERRUPT UNIT
INT. VECTOR POINTER INT. CONTROL REGISTER
COMPARE LOGIC INTERNAL TRIGGER CONTROL LOGIC EXTERNAL TRIGGER DATA REGISTER 7 DATA REGISTER 6 DATA REGISTER 5 DATA REGISTER 4 DATA REGISTER 3 DATA REGISTER 2 DATA REGISTER 1 DATA REGISTER 0
COMPARE RESULT REGISTER THRESHOLD REGISTER 7U THRESHOLD REGISTER 7L THRESHOLD REGISTER 6U THRESHOLD REGISTER 6L AIN 7 AIN 6 AIN 5 AIN 4 AIN 3 AIN 2 AIN 1 AIN 0
CONVERSION RESULT
ANALOG MUX
SUCCESSIVE APPROXIMATION A/D CONVERTER
CONTROL REG.
AUTOSCAN LOGIC
VA00223
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ANALOG TO DIGITAL CONVERTER (Cont'd) Single and continuous conversion modes are available. Conversion may be triggered by an external signal or, internally, by the Multifunction Timer. Conversion Time The maximum conversion time is as follows: 138 * FDF * INTCLK The minimum sample time is: 84 * FDF * INTCLK where FDF is the Frequency Division Factor (refer to the PR bit description in the CCR register). For instance, if PR[2:0] = 100 -> FDF = 8 then the conversion time is: 138 * 8 * INTCLK = 1104 and the sample time is 84 * 8 * INTCLK = 672 INTCLK. A Power-Down programmable bit allows the ADC to be set in low-power idle mode. The ADC's Interrupt Unit provides two maskable channels (Analog Watchdog and End of Conversion) with hardware fixed priority, and up to 7 programmable priority levels. CAUTION: ADC INPUT PIN CONFIGURATION The input Analog channel is selected by using the I/O pin Alternate Function setting (PXC2, PXC1, PXC0 = 1,1,1) as described in the I/O ports section. The I/O pin configuration of the port connected to the A/D converter is modified in order to prevent the analog voltage present on the I/O pin from causing high power dissipation across the input buffer. Deselected analog channels should also be maintained in Alternate function configuration for the same reason. 7.6.2 Functional Description 7.6.2.1 Operating Modes Two operating modes are available: Continuous Mode and Single Mode. To enter one of these modes it is necessary to program the CONT bit of the Control Logic Register. The Continuous Mode is selected when CONT is set, while Single Mode is selected when CONT is reset. Both modes operate in AUTOSCAN configuration, allowing sequential conversion of the input channels. The number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into the Control Register (SC2, SC1, SC0 bits). As each conversion is completed, the channel number is automatically incremented, up to channel 7. For example, if SC2, SC1, SC0 are set to 0,1,1, conversion will proceed from channel 3 to channel 7, whereas, if
SC2, SC1, SC0 are set to 1,1,1, only channel 7 will be converted. When the ST bit of the Control Logic Register is set, either by software or by hardware (by an internal or external synchronisation trigger signal), the analog inputs are sequentially converted (from the first selected channel up to channel 7) and the results are stored in the relevant Data Registers. In Single Mode (CONT = "0"), the ST bit is reset by hardware following conversion of channel 7; an End of Conversion (ECV) interrupt request is issued and the ADC waits for a new start event. In Continuous Mode (CONT = "1"), a continuous conversion flow is initiated by the start event. When conversion of channel 7 is complete, conversion of channel 's' is initiated (where 's' is specified by the setting of the SC2, SC1 and SC0 bits); this will continue until the ST bit is reset by software. In all cases, an ECV interrupt is issued each time channel 7 conversion ends. When channel 'i' is converted ('s' <'i' <7), the related Data Register is reloaded with the new conversion result and the previous value is lost. The End of Conversion (ECV) interrupt service routine can be used to save the current values before a new conversion sequence (so as to create signal sample tables in the Register File or in Memory). 7.6.2.2 Triggering and Synchronisation In both modes, conversion may be triggered by internal or external conditions; externally this may be tied to EXTRG, as an Alternate Function input on an I/O port pin, and internally, it may be tied to INTRG, generated by a Multifunction Timer peripheral. Both external and internal events can be separately masked by programming the EXTG/ INTG bits of the Control Logic Register (CLR). The events are internally ORed, thus avoiding potential hardware conflicts. However, the correct procedure is to enable only one alternate synchronisation condition at any time. The effect either of these synchronisation modes is to set the ST bit by hardware. This bit is reset, in Single Mode only, at the end of each group of conversions. In Continuous Mode, all trigger pulses after the first are ignored. The synchronisation sources must be at a logic low level for at least the duration of one INTCLK cycle and, in Single Mode, the period between trigger pulses must be greater than the total time required for a group of conversions. If a trigger occurs when the ST bit is still set, i.e. when conversion is still in progress, it will be ignored.
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ANALOG TO DIGITAL CONVERTER (Cont'd) On devices where two A/D Converters are present they can be triggered from the same source.
Converter A/D 0 A/D 1 External Trigger EXTRG pin On Chip Event (Internal trigger) MFT 0
7.6.2.3 Analog Watchdogs Two internal Analog Watchdogs are available for highly flexible automatic threshold monitoring of external analog signal levels. Analog channels 6 and 7 monitor an acceptable voltage level window for the converted analog inputs. The external voltages applied to inputs 6 and 7 are considered normal while they remain below their respective Upper thresholds, and above or at their respective Lower thresholds. When the external signal voltage level is greater than, or equal to, the upper programmed voltage limit, or when it is less than the lower programmed voltage limit, a maskable interrupt request is generated and the Compare Results Register is updated in order to flag the threshold (Upper or Lower) and channel (6 or 7) responsible for the interrupt. The four threshold voltages are user programmable in dedicated registers (08h to 0Bh) of the ADC register page. Only the 4 MSBs of the Compare Results Register are used as flags, each of the four MSBs being associated with a threshold condition. Figure 79. A/D Trigger Source
Following a reset, these flags are reset. During normal ADC operation, the CRR bits are set, in order to flag an out of range condition and are automatically reset by hardware after a software reset of the Analog Watchdog Request flag in the ICR Register. 7.6.2.4 Power Down Mode Before enabling an A/D conversion, the POW bit of the Control Logic Register must be set; this must be done at least 60s before the first conversion start, in order to correctly bias the analog section of the converter circuitry. When the ADC is not required, the POW bit may be reset in order to reduce the total power consumption. This is the reset configuration, and this state is also selected automatically when the ST9 is placed in Halt Mode (following the execution of the halt instruction).
Analog Voltage Upper threshold Normal Area (Window Guarded) Lower threshold
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ANALOG TO DIGITAL CONVERTER (Cont'd) Figure 80. Application Example: Analog Watchdog used in Motorspeed Control
7.6.3 Interrupts The ADC provides two interrupt sources: - End of Conversion - Analog Watchdog Request The A/D Interrupt Vector Register (IVR) provides hardware generated flags which indicate the interrupt source, thus allowing automatic selection of the correct interrupt service routine.
Analog Watchdog Request 7 X X X X X X 0 0 0
Lower Word Address
End of Conv. Request
7 X X X X X X 1
0 0
Upper Word Address
The A/D Interrupt vector should be programmed by the User to point to the first memory location in
the Interrupt Vector table containing the base address of the four byte area of the interrupt vector table in which the address of the A/D interrupt service routines are stored. The Analog Watchdog Interrupt Pending bit (AWD, ICR.6), is automatically set by hardware whenever any of the two guarded analog inputs go out of range. The Compare Result Register (CRR) tracks the analog inputs which exceed their programmed thresholds. When two requests occur simultaneously, the Analog Watchdog Request has priority over the End of Conversion request, which is held pending. The Analog Watchdog Request requires the user to poll the Compare Result Register (CRR) to determine which of the four thresholds has been exceeded. The threshold status bits are set to flag an out of range condition, and are automatically reset by hardware after a software reset of the Analog Watchdog Request flag in the ICR Register. The interrupt pending flags, ECV and AWD, should be reset by the user within the interrupt service routine. Setting either of these two bits by software will cause an interrupt request to be generated.
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7.6.4 Register Description DATA REGISTERS (DiR) The conversion results for the 8 available channels are loaded into the 8 Data registers following conversion of the corresponding analog input. CHANNEL 0 DATA REGISTER (D0R) R240 - Read/Write Register Page: 63 Reset Value: undefined
7 D0.7 D0.6 D0.5 D0.4 D0.3 D0.2 D0.1 0 D0.0
CHANNEL 4 DATA REGISTER (D4R) R244 - Read/Write Register Page: 63 Reset Value: undefined
7 D4.7 D4.6 D4.5 D4.4 D4.3 D4.2 D4.1 0 D4.0
Bit 7:0 = D4.[7:0]: Channel 4 Data CHANNEL 5 DATA REGISTER (D5R) R245 - Read/Write Register Page: 63 Reset Value: undefined
7 D5.7 D5.6 D5.5 D5.4 D5.3 D5.2 D5.1 0 D5.0
Bit 7:0 = D0.[7:0]: Channel 0 Data CHANNEL 1 DATA REGISTER (D1R) R241 - Read/Write Register Page: 63 Reset Value: undefined
7 D1.7 D1.6 D1.5 D1.4 D1.3 D1.2 D1.1 0 D1.0
Bit 7:0 = D5.[7:0]: Channel 5 Data CHANNEL 6 DATA REGISTER (D6R) R246 - Read/Write Register Page: 63 Reset Value: undefined
7 D6.7 D6.6 D6.5 D6.4 D6.3 D6.2 D6.1 0 D6.0
Bit 7:0 = D1.[7:0]: Channel 1 Data CHANNEL 2 DATA REGISTER (D2R) R242 - Read/Write Register Page: 63 Reset Value: undefined
7 D2.7 D2.6 D2.5 D2.4 D2.3 D2.2 D2.1 0 D2.0
Bit 7:0 = D6.[7:0]: Channel 6 Data CHANNEL 7 DATA REGISTER (D7R) R247 - Read/Write Register Page: 63 Reset Value: undefined
7 D7.7 D7.6 D7.5 D7.4 D7.3 D7.2 D7.1 0 D7.0
Bit 7:0 = D2.[7:0]: Channel 2 Data CHANNEL 3 DATA REGISTER (D3R) R243 - Read/Write Register Page: 63 Reset Value: undefined
7 D3.7 D3.6 D3.5 D3.4 D3.3 D3.2 D3.1 0 D3.0
Bit 7:0 = D7.[7:0]: Channel 7 Data
Bit 7:0 = D3.[7:0]: Channel 3 Data
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REGISTER DESCRIPTION (Cont'd) LOWER THRESHOLD REGISTERS (LTiR) The two Lower Threshold registers are used to store the user programmable lower threshold 8-bit values, to be compared with the current conversion results, thus setting the lower window limit. CHANNEL 6 LOWER THRESHOLD REGISTER (LT6R) R248 - Read/Write Register Page: 63 Reset Value: undefined
7 0
The two Upper Threshold registers are used to store the user programmable upper threshold 8-bit values, to be compared with the current conversion results, thus setting the upper window limit. CHANNEL 6 UPPER THRESHOLD REGISTER (UT6R) R250 - Read/Write Register Page: 63 Reset Value: undefined
7 0
LT6.7 LT6.6 LT6.5 LT6.4 LT6.3 LT6.2 LT6.1 LT6.0
UT6.7 UT6.6 UT6.5 UT6.4 UT6.3 UT6.2 UT6.1 UT6.0
Bit 7:0 = LT6.[7:0]: Channel 6 Lower Threshold CHANNEL 7 LOWER THRESHOLD REGISTER (LT7R) R249 - Read/Write Register Page: 63 Reset Value: undefined
7 0
Bit 7:0 = UT6.[7:0]: Channel 6 Upper Threshold value CHANNEL 7 UPPER THRESHOLD REGISTER (UT7R) R251 - Read/Write Register Page: 63 Reset Value: undefined
7 0
LT7.7 LT6.7 LT7.5 LT7.4 LT7.3 LT7.2 LT7.1 LT7.0 UT7.7 UT6.7 UT7.5 UT7.4 UT7.3 UT7.2 UT7.1 UT7.0
Bit 7:0 = LT7.[7:0]: Channel 7 Lower Threshold UPPER THRESHOLD REGISTERS (UTIR) Bit 7:0 = UT7.[7:0]: Channel 7 Upper Threshold value
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REGISTER DESCRIPTION (Cont'd) COMPARE RESULT REGISTER (CRR) R252 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh)
7 C7U C6U C7L C6L X PR2 PR1 0 PR0
Note: Any software reset request of the ICR, will also cause all the compare status bits to forced by hardware to zero, in order to prevent possible overwriting if an interrupt request occurs between reset and the Interrupt request software reset. Bit 3 = undefined, return '1' when red. Bit 2:0 = PR[2:0]: Clock divider bits These bits enable a frequency division factor depending on the value stored: Table 30. Frequency Division Factors PR[2:0] bits
111 110 101 100 011 010 001 000
The result of the comparison between the current value of data registers 6 and 7 and the threshold registers is stored in the 4 most significant bits of this register. Bit 7 = C7U: Compare Reg 7 Upper threshold Set when converted data is greater than or equal to the threshold value. Not affected otherwise. Bit 6 = C6U: Compare Reg 6 Upper threshold Set when converted data is greater than or equal to the threshold value. Not affected otherwise. Bit 5 = C7L: Compare Reg 7 Lower threshold Set when converted data is less than the threshold value. Not affected otherwise. Bit 4 = C6L: Compare Reg 6 Lower threshold Set when converted data is less than the threshold value. Not affected otherwise. These bits should be reset at the end of the "Out of Range" interrupt service routine.
Freq. Div. Factor (FDF)
1 4 6 8 10 12 14 16
Max. conMin. samversion pling time time (INTCLK) (INTCLK)
138 552 828 1104 1380 1656 1932 2208 84 336 504 672 840 1008 1176 1344
Warning: If the prescaler programming value is changed during a conversion, the user has to restart the conversion (i.e. simply rewriting the CLR register with the same value).
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REGISTER DESCRIPTION (Cont'd) CONTROL LOGIC REGISTER (CLR) The Control Logic Register (CLR) manages the ADC's logic. Writing to this register will cause the current conversion to be aborted and the autoscan logic to be re-initialized. CLR is programmable as follows: CONTROL LOGIC REGISTER (CLR) R253 - Read/Write Register Page: 63 Reset Value: 0000 0000 (00h)
7 SC2 SC1 SC0 EXTG INTG POW CONT 0 ST
Bit 7:5 = SC[2:0]: Start Conversion Address. These 3 bits define the starting analog input channel (Autoscan mode). The first channel addressed by SC[2:0] is converted, then the channel number is incremented for the successive conversion, until channel 7 (111) is converted. When SC2, SC1 and SC0 are all set, only channel 7 will be converted. Bit 4 = EXTG: External Trigger Enable. This bit is set and cleared by software. 0: External trigger disabled. 1: External trigger enabled. Allows a conversion sequence to be started on the subsequent edge of the external signal applied to the EXTRG pin (when enabled as an Alternate Function). Bit 3 = INTG: Internal Trigger Enable. This bit is set and cleared by software. 0: Internal trigger disabled. 1: Internal trigger enabled. Allows a conversion sequence to be started, synchronized by an internal signal (On-chip Event signal) from a Multifunction Timer peripheral.
Both External and Internal Trigger inputs are internally ORed, thus avoiding Hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. Note: The effect of either synchronization mode is to set the START/STOP bit, which is reset by hardware when in SINGLE mode, at the end of each sequence of conversions. Requirements: The External Synchronisation Input must receive a low level pulse wider than an INTCLK period and, for both External and On-Chip Event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. Bit 2 = POW: Power Up/Power Down. This bit is set and cleared by software. 0: Power down mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: Power up mode: the A/D converter logic and analog circuitry is enabled. Bit 1 = CONT: Continuous/Single. 0: Single Mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the ST bit is set by software. 1: Continuous Mode: the first sequence of conversions is started, either by software (by setting the ST bit), or by hardware (on an internal or external trigger, depending on the setting of the INTG and EXTG bits); a continuous conversion sequence is then initiated. Bit 0 = ST: Start/Stop. 0: Stop conversion. When the A/D converter is running in Single Mode, this bit is hardware reset at the end of a sequence of conversions. 1: Start a sequence of conversions.
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REGISTER DESCRIPTION (Cont'd) INTERRUPT CONTROL REGISTER (AD_ICR) The Interrupt Control Register contains the three priority level bits, the two source flags, and their bit mask: INTERRUPT CONTROL REGISTER (AD_ICR) R254 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh)
7 ECV AWD ECI AWDI X PL2 PL1 0 PL0
Bit 4 = AWDI: Analog Watchdog Interrupt Enable. This bit masks or enables the Analog Watchdog interrupt request. 0: Mask Analog Watchdog interrupts 1: Enable Analog Watchdog interrupts Bit 3 = Reserved. Bit 2:0 = PL[2:0]: A/D Interrupt Priority Level. These three bits allow selection of the Interrupt priority level for the ADC. INTERRUPT VECTOR REGISTER (AD_IVR) R255 - Read/Write Register Page: 63 Reset Value: xxxx xx10 (x2h)
7 V7 V6 V5 V4 V3 V2 W1 0 0
Bit 7 = ECV: End of Conversion. This bit is automatically set by hardware after a group of conversions is completed. It must be reset by the user, before returning from the Interrupt Service Routine. Setting this bit by software will cause a software interrupt request to be generated. 0: No End of Conversion event occurred 1: An End of Conversion event occurred Bit 6 = AWD: Analog Watchdog. This is automatically set by hardware whenever either of the two monitored analog inputs goes out of bounds. The threshold values are stored in registers F8h and FAh for channel 6, and in registers F9h and FBh for channel 7 respectively. The Compare Result Register (CRR) keeps track of the analog inputs exceeding the thresholds. The AWD bit must be reset by the user, before returning from the Interrupt Service Routine. Setting this bit by software will cause a software interrupt request to be generated. 0: No Analog Watchdog event occurred 1: An Analog Watchdog event occurred Bit 5 = ECI: End of Conversion Interrupt Enable. This bit masks the End of Conversion interrupt request. 0: Mask End of Conversion interrupts 1: Enable End of Conversion interrupts
Bit 7:2 = V[7:2]: A/D Interrupt Vector. This vector should be programmed by the User to point to the first memory location in the Interrupt Vector table containing the starting addresses of the A/D interrupt service routines. Bit 1 = W1: Word Select. This bit is set and cleared by hardware, according to the A/D interrupt source. 0: Interrupt source is the Analog Watchdog, pointing to the lower word of the A/D interrupt service block (defined by V[7:2]). 1:Interrupt source is the End of Conversion interrupt, thus pointing to the upper word. Note: When two requests occur simultaneously, the Analog Watchdog Request has priority over the End of Conversion request, which is held pending. Bit 0 = Reserved. Forced by hardware to 0.
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ST92141 - ELECTRICAL CHARACTERISTICS
8 ELECTRICAL CHARACTERISTICS
This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VIN and VO be higher than V SS and lower than V DD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or V SS). Power Considerations. The average chip-junction temperature, TJ, in Celsius can be obtained from: TJ = TA + P D x RthJA Ambient Temperature. Where: TA = RthJA = Package thermal resistance (junction-to ambient). PD = PINT + PPORT. PINT = IDD x VDD (chip internal power). PPORT = Port power dissipation (determined by the user)
Value - 0.3 to 6.5 up to VDD + 0.3 VSS - 0.3 to VDD + 0.3 AVSS to AVDD 2000 - 55 to +150 +/- 10 +/- 100 V V V C mA mA
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol VDD AVDD AVSS VIN VAIN ESD TSTG IINJ Supply Voltage A/D Converter Analog Reference A/D Converter VSS Input Voltage (standard I/O pins) Analog Input Voltage (A/D Converter) ESD susceptibility Storage Temperature Pin Injection Current - Digital and Analog Input Maximum Accumulated Pin Injection Current Parameter Unit V V
Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to V SS=0. (1) AVDD can be shut down while the A/D Converter is not in use.
THERMAL CHARACTERISTICS
Symbol RthJA Package PDIP32Sh PSO34Sh Value 60 75 Unit C/W
RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD AVDD fINTCLK Parameter Operating Temperature Operating Supply Voltage(1) Analog Supply Voltage Internal Clock Frequency @ 4.5V - 5.5V Value Min -40 4.5 0 0
(2)
Max 85 5.5 VDD + 0.3 25
Unit C V V MHz
Note: (1) Device is reset whenever Supply Voltage is below LVD Thresholds (2) 1MHz when A/D is used with its internal Prescaler programmed to 1.
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DC ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, unless otherwise specified)
Symbol Parameter Input High Level Standard Schmitt Trigger VIH P5[7:2] Input High Level High Hyst. Schmitt Trigger P5[1:0]-P3[6:0]-TACHO Input Low Level Standard Schmitt Trigger VIL P5[7:2] Input Low Level High Hyst. Schmitt Trigger P5[1:0]-P3[6:0]-TACHO Input Hysteresis (2) Standard Schmitt Trigger VHYS P5[7:2] Input Hysteresis (2) High Hyst. Schmitt Trigger P5[1:0]-P3[6:0]-TACHO Output High Level High Current Pins P3.5-P3.6-P5.0-P5.2 VOH Output High Level Standard Current Pins P3[4:0]-P3.7-P5.1-P5[7:3]UH-UL-VH-VL-WH-WL Push Pull, IOL=2mA EMR1 Register - BSZ bit = 0 (3) Push Pull, IOL=8mA, EMR1 Register - BSZ bit = 1 (3) Push Pull, IOL=20mA, EMR1 Register - BSZ bit = 1 (3) Push Pull, IOH= - 2mA VDD - 0.8 V Push Pull, IOH= - 2mA EMR1 Register - BSZ bit = 0 (3) Psh Pull, IOH= - 8mA EMR1 Register - BSZ bit = 1 (3) VDD - 0.8 VDD - 0.8 V V 1.5 V 0.5 V - 0.3 0.8 V - 0.3 0.8 V 0.8VDD VDD + 0.3 Comment Value Min 0.7VDD Typ(1) Max VDD + 0.3 Unit
V
V
0.4 0.4 3
V V V
Output Low Level High Current Pins P3.5-P3.6-P5.0-P5.2 VOL Output Low Level Standard Current Pins P3[4:0]-P3.7-P5.1-P5[7:3]UH-UL-VH-VL-WH-WL IWPU ILKIO ILKA/D Weak Pull-up Current P5[7:0]-P3[6:0] I/O Pin Input Leakage A/D Conv. Input Leakage
Push Pull, IOL=2mA
0.4
V
Bidirectional Weak Pull-up VOL = 0V Input/Tri-State, 0V < VIN < VDD
50 - 10 -1
600 + 10 +1
A A A
Note: (1) Unless otherwise stated, typical data are based on T A=25C and VDD=5V. They are only reported for design guidelines - not tested in production. (2) Data based on characterization results - not tested in production. (3) For a description of the EMR1 Register - BSZ bit refer to the Device Configuration Registers Chapter.
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LOW VOLTAGE DETECTOR DC CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, unless otherwise specified)
Symbol VLVDR VLVDF VLVDHyst IDDLVD Parameter Reset release Threshold Reset generation Threshold Hysteresis(2) Supply Current Test Conditions VDD rise - Halt Mode VDD fall - Halt Mode Halt Mode Halt Mode 3.4 200 250 Min Typ(1) Max 4.2 Unit V V mV A
Note: (1) Unless otherwise stated, typical data are based on T A=25C and VDD=5V. They are only reported for design guidelines - not tested in production. (2) Data based on characterization results - not tested in production
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AC ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, unless otherwise specified)
Symbol IDDRUN IDDWFI IDDLPWFI IDDHALT Parameter Run Mode Current(2) WFI Mode Current Low Power WFI Mode Current HALT Mode Current INTCLK 25 MHz 25 MHz 125 kHz Typ(1) Max 50 15 2 250 Unit mA mA mA A
Note: All I/O Ports are configured to a static value of VDD or VSS, external clock pin (OSCIN) is driven by square wave external clock. (1) Unless otherwise stated, typical data are based on TA=25C and VDD=5V. They are only reported for design guidelines - not tested in production. (2) CPU running with memory access, all peripherals switched off.
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EXTERNAL INTERRUPT TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N 1 2 3 4 Symbol TwINTLR TwINTHR TwINTHF TwINTLF Parameter Low Level Pulse Width in Rising Edge Mode High Level Pulse Width in Rising Edge Mode High Level Pulse Width in Falling Edge Mode Low Level Pulse Width in Falling Edge Mode Value (Note) Formula(1) Tck+10 Tck+10 Tck+10 Tck+10 Min 50 50 50 50 Max Unit ns ns ns ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. The value in the right hand two columns show the timing minimum and maximum for an internal clock at 25MHz (INTCLK). Measurement points are taken with reference to VIH-VIH for positive pulse and V IL-VIL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled.
EXTERNAL INTERRUPT TIMING
n=0,6
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WAKE-UP MANAGEMENT TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N 1 2 3 4 Symbol TwWKPLR TwWKPHR TwWKPHF TwWKPLF Parameter Low Level Pulse Width in Rising Edge Mode High Level Pulse Width in Rising Edge Mode High Level Pulse Width in Falling Edge Mode Low Level Pulse Width in Falling Edge Mode Value (Note) Formula(1) Tck+10 Tck+10 Tck+10 Tck+10 Min 50 50 50 50 Max Unit ns ns ns ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. The value in the right hand two columns show the timing minimum and maximum for an internal clock at 25MHz (INTCLK). The given data are related to Wake-up Management Unit used in External Interrupt mode. Measurement points are taken with reference to VIH-VIH for positive pulse and V IL-VIL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled.
WAKE-UP MANAGEMENT TIMING
WKUPn
n=0-3
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ST92141 - ELECTRICAL CHARACTERISTICS
RCCU CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
Symbol VIHRS VILRS VHYRS ILKRS Parameter RESET Input High Level RESET Input Low Level RESET Input Hysteresis(2) RESET Pin Input Leakage 0V < VIN < VDD - 10 Comment Value (Note) Min 0.7VDD - 0.3 900 + 10 Typ(1) Max VDD + 0.3 0.3VDD Unit V V mV A
Note: (1) Unless otherwise stated, typical data are based on T A=25C and VDD=5V. They are only reported for design guidelines - not tested in production. (2) Data based on characterization results - not tested in production
RCCU TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
Symbol TFRS TNFRS TRSPH
(1)
Parameter RESET Input Filtered Pulse RESET Input not Filtered Pulse RESET Phase duration STOP Restart duration
Comment
Value (Note) Min Typ Max 50 20 20478 x Tosc 10239 x Tosc 20478 x Tosc
Unit ns s
s s
TSTR
DIV2 = 0 DIV2 = 1
Note: (1) Depending on the delay between rising edge of RESET pin and the first rising edge of CLOCK1, the value can differ from the typical value for +/- 1 CLOCK1 cycle. Legend: Tosc = OSCIN period
PLL CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
Symbol FVCO
TPLK
Parameter
VCO Operating Frequency Lock-in Time PLL Jitter
Comment
Value (Note) Min
6 0
Typ
Max
25 1000 x Tosc 1.2 (1)
Unit
MHz s ns
Note: (1) Measured with PLL output clock frequency equal to 25MHz. Data based on characterization results - not tested in production. Legend: Tosc = OSCIN period
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ST92141 - ELECTRICAL CHARACTERISTICS
OSCILLATOR CHARACTERISTICS (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
Symbol FOSC gm VIHCK VILCK ILKOS TSTUP Parameter Crystal Frequency Oscillator Clock Input High Level Clock Input Low Level OSCIN/OSCOUT Pins Input Leakage Oscillator Start-up Time External Clock External Clock 0V < VIN < VDD (HALT/STOP) Comment Fundamental mode crystal only Value (Note) Min 3 0.6 0.8VDD - 0.3 - 10 6(2) 1.4 Typ(1) Max 5 2.5 VDD + 0.3 0.2VDD + 10 Unit MHz mA/V V V A ms
Note: (1) Unless otherwise stated, typical data are based on T A=25C and VDD=5V. They are only reported for design guidelines - not tested in production. (2) Typical value with OSCIN=5MHz, CL=33pF on OSCIN-OSCOUT, T A=25C, VDD=5V. The value depends on resonator quality as well.
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ST92141 - ELECTRICAL CHARACTERISTICS
WATCHDOG TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, Push-pull output configuration, unless otherwise specified)
N Symbol Parameter Value (Note) Formula(1) 4 x (Psc+1) x (Cnt+1) x Tck 1 TwWDOL WDOUT Low Pulse Width (Psc+1) x (Cnt+1) x TWDIN with TWDIN 8 x Tck 4 x (Psc+1) x (Cnt+1) x Tck 2 TwWDOH WDOUT High Pulse Width (Psc+1) x (Cnt+1) x TWDIN with TWDIN 8 x Tck 3 4 TwWDIL TwWDIH WDIN High Pulse Width WDIN Low Pulse Width 4 x Tck + 10 4 x Tck +10 Min 160 2.69 320 160 2.69 320 170 170 Max Unit ns s ns ns s ns ns ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 25MHz, with minimum and maximum prescaler value and minimum and maximum counter value. Measurement points are taken with reference to VIH-VIH / VOH -VOH for positive pulse and V IL-VIL / VOL-VOL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. Psc = Watchdog Prescaler Register content (WDTPR): from 0 to 255 Cnt = Watchdog Counter Registers content (WDTRH,WDTRL): from 0 to 65535 TWDIN = Watchdog Input signal period (WDIN)
WATCHDOG TIMING
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ST92141 - ELECTRICAL CHARACTERISTICS
STANDARD TIMER TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, Push-pull output configuration, unless otherwise specified)
N Symbol Parameter Value (Note) Formula(1) 4 x (Psc+1) x (Cnt+1) x Tck 1 TwSTOL STOUT Low Pulse Width (Psc+1) x (Cnt+1) x TSTIN with TSTIN 8 x Tck 4 x (Psc+1) x (Cnt+1) x Tck 2 TwSTOH STOUT High Pulse Width (Psc+1) x (Cnt+1) x TSTIN with TSTIN 8 x Tck 3 4 TwSTIL TwSTIH STIN High Pulse Width STIN Low Pulse Width 4 x Tck + 10 4 x Tck + 10 Min 160 2.69 320 160 2.69 320 170 170 Max Unit ns s ns ns s ns ns ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 25MHz, with minimum and maximum prescaler value and minimum and maximum counter value. Measurement points are taken with reference to VIH-VIH / VOH -VOH for positive pulse and V IL-VIL / VOL-VOL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. Psc = Standard Timer Prescaler Register content (STP): from 0 to 255 Cnt = Standard Timer Counter Registers content (STH,STL): from 0 to 65535 TSTIN = Standard Timer Input signal period (STIN).
STANDARD TIMER TIMING
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ST92141 - ELECTRICAL CHARACTERISTICS
EXTENDED FUNCTION TIMER EXTERNAL TIMING TABLE (VDD = 5V 10%, TA = -40C to +105C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N 1 2 3 4 5 6 Symbol TwPEWL TwPEWH TwPIWL TwPIWH TwECKD TwEICD Parameter External Clock low pulse width (EXTCLK) External Clock high pulse width (EXTCLK) Input Capture low pulse width (ICAPx) Input Capture high pulse width (ICAPx) Distance between two active edges on EXTCLK Distance between two active edges on ICAPx Value Formula(1) 2 x Tck + 10 2 x Tck + 10 2 x Tck + 10 2 x Tck + 10 4 x Tck + 10 2 x Tck x Prsc +10 Min 90 90 90 90 170 170 Unit ns ns ns ns ns ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 25MHz, and minimum prescaler factor (=2). Measurement points are taken with reference to VIH-VIH for positive pulse and V IL-VIL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. Prsc = Prescaler factor defined by Extended Function Timer Clock Control bits (CC1,CC0) on control register CR2 (values: 2,4,8).
EXTENDED FUNCTION TIMER EXTERNAL TIMING
1
2
EXTCLK
5
3
4
ICAPA ICAPB
6
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ST92141 - ELECTRICAL CHARACTERISTICS
SPI TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
Value(1) N Symbol Parameter Master Slave Master Slave Slave Slave Master Slave Master Slave Master Slave Master Slave Condition Min fSPI 1 2 3 4 5 6 7 8 9 10 11 12 13 tSPI tLead tLag tSPI_H tSPI_L tSU tH tA tDis tV tHold tRise tFall SPI frequency SPI clock period Enable lead time Enable lag time Clock (SCK) high time Clock (SCK) low time Data set-up time Data hold time (inputs) Access time (time to data active from high impedance state) Disable time (hold time to high impedance state) Data valid Data hold time (outputs) fINTCLK / 128 0 4 x Tck 2 x Tck 40 40 80 90 80 90 40 40 40 40 0 Slave 240 Master (before capture edge) Slave (after enable edge) Master (before capture edge) Slave (after enable edge) Tck / 4 120 Tck / 4 0 100 100 100 100 ns ns ns ns ns ns s ns s 120 Max fINTCLK / 4 fINTCLK / 2 MHz ns ns ns ns ns ns ns ns Unit
Rise time Outputs: SCK,MOSI,MISO (20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS Fall time Outputs: SCK,MOSI,MISO (70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
Note: Measurement points are taken with reference to VIH-VIH / VOH -VOH for positive pulse and V IL-VIL / VOL-VOL for negative pulse (1) Values guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled.
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ST92141 - ELECTRICAL CHARACTERISTICS
SPI Master Timing Diagram CPHA=0, CPOL=0
SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) MOSI (OUTPUT) 6 10 D7-IN 7 D7-OUT 11 5 D6-IN D6-OUT D0-IN D0-OUT VR000109 1 13 12
SPI Master Timing Diagram CPHA=0, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 5 6 10 D7-IN 7 D7-OUT 11 4 D6-IN D6-OUT D0-IN D0-OUT VR000110 12
SPI Master Timing Diagram CPHA=1, CPOL=0
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 4 6 10 5 D7-OUT 7 D7-IN 11 D6-IN D0-IN VR000107 D6-OUT D0-OUT 12
SPI Master Timing Diagram CPHA=1, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 12 5 6 10 4 D7-IN 7 D7-OUT 11 D6-IN D6-OUT D0-IN D0-OUT VR000108 13
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ST92141 - ELECTRICAL CHARACTERISTICS
SPI Slave Timing Diagram CPHA=0, CPOL=0
SS (INPUT) 2 SCK (INPUT) MISO HIGH-Z (OUTPUT) 8 MOSI (INPUT) 6 1 13 4 D7-OUT 10 D7-IN 7 VR000113 D6-IN 5 D6-OUT 11 D0-IN D0-OUT 9 12 3
SPI Slave Timing Diagram CPHA=0, CPOL=1
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 1 12 5 D7-OUT 10 D7-IN 7 VR000114 D6-IN 4 D6-OUT 11 D0-IN D0-OUT 9 13 3
SPI Slave Timing Diagram CPHA=1, CPOL=0
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 6 8 D7-IN 7 VR000111 4 5 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 13 12 3
SPI Slave Timing Diagram CPHA=1, CPOL=1
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 6 8 D7-IN 7 VR000112 5 4 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 12 13 3
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ST92141 - ELECTRICAL CHARACTERISTICS
A/D EXTERNAL TRIGGER TIMING TABLE (VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N Symbol 1 2 3 4 TwLOW TwHIGH TwEXT TdSTR Parameter External trigger pulse width External trigger pulse distance External trigger active edges distance EXTRG falling edge and first conversion start Value (Note) Formula(1) 1.5 x Tck 1.5 x Tck 138 x n x FDF x Tck 0.5 x Tck 1.5 x Tck Min. 60 60 n x FDF x 5.52 20 Max. 60 Unit ns ns s ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 25MHz. Measurement points are taken with reference to VIH-VIH for positive pulse and V IL-VIL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2*OSCIN period when OSCIN is divided by 2; OSCIN period / PLL factor when the PLL is enabled. n = number of autoscanned channels (1 n 8) FDF = Frequency Division Factor (ADC prescaler factor), refer to section 7.6.1 on page 147
A/D EXTERNAL TRIGGER TIMING
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ST92141 - ELECTRICAL CHARACTERISTICS
A/D ANALOG SPECIFICATIONS (VDD = 5V, TA = 25C, fINTCLK = 25MHz, unless otherwise specified)
Parameter Conversion time Sample time Power-up time Resolution Monotonicity No missing codes Zero input reading Full scale reading Offset error Gain error Diff. Non Linearity error (DNL) Int. Non Linearity error (INL) Absolute Accuracy Input Resistance Hold Capacitance Input Leakage 2.7 1.4 1 00 FF 1 1 1 1 2 8 Typical Minimum 138 85 60 8 GUARANTEED GUARANTEED Hex Hex LSBs LSBs LSBs LSBs LSBs k pF A
(6) (6) (1)(4)(6) (4)(6) (4)(6) (4)(6) (4)(6) (3)(5)(6) (5)(6) (6)
Maximum
Units (1) INTCLK INTCLK s bits
Notes
(2)(6) (6) (6)
Note: (1) "1LSBideal" has a value of AV DD/256 (2) Including sample time (3) This is the internal series resistance before the sampling capacitor (4) This is a typical expected value, but not a tested production parameter. If V(i) is the value of the i-th transition level (0 i 254), the performance of the A/D converter has been evaluated as follows: OFFSET ERROR= deviation between the actual V(0) and the ideal V(0) (=1/2 LSB) GAIN ERROR= deviation between the actual V(254) and the ideal V(254) - V(0) (ideal V(254)=AV DD-3/2 LSB) DNL ERROR= max {[V(i) - V(i-1)]/LSB - 1} INL ERROR= max {[V(i) - V(0)]/LSB - i} ABS. ACCURACY= overall max conversion error (5) Simulated value. (6) The specified values are guaranteed only if an overload condition occurs on a maximum of 2 non-selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA.
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ST92141 - ELECTRICAL CHARACTERISTICS
Figure 81. A/D Conversion Characteristics
Offset Error OSE 255 254 253 252 251 250 ( 2)
code out
Gain Error GE
7 ( 1) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 250 251 252 253 254 255 256
Vin(A) (LSBideal)
(5) (4) (3) 1 LSB (ideal)
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
Offset Error OSE
VR02133A
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ST92141 - ELECTRICAL CHARACTERISTICS
IMC TIMING TABLE VDD = 5V 10%, TA = -40C to +85C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N 1 2 3 4 5 6 7 8 9 Symbol TwTACLR TwTACHR TwTACHF TwTACLF TwNMILR TwNMIHR TwNMIHF TwNMILF TdPHZ Parameter Tacho Low Level Minimum Pulse Width in Rising Edge Mode Tacho High Level Minimum Pulse Width in Rising Edge Mode Tacho High Level Minimum Pulse Width in Falling Edge Mode Tacho Low Level Minimum Pulse Width in Falling Edge Mode NMI Low Level Minimum Pulse Width in Rising Edge Mode NMI High Level Minimum Pulse Width in Rising Edge Mode NMI High Level Minimum Pulse Width in Falling Edge Mode NMI Low Level Minimum Pulse Width in Falling Edge Mode Delay from NMI to Phases in High Impedance Value (Note) Formula(1) Tck Tck Tck Tck Min 40 40 40 40 1000 1000 1000 1000 1000 Max Unit ns ns ns ns ns ns ns ns ns
Note: The value in the left hand column shows the formula used to calculate the minimum or maximum timing from the oscillator clock period. The value in the right hand two columns show the minimum and maximum timing for an internal clock at 25MHz (INTCLK). Measurement points are taken with reference to VIH-VIH for positive pulse and V IL-VIL for negative pulse (1) Formula guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled.
IMC TIMING
TACHO
NMI
5
6
7
8
/ NMI
UH/UL/VH/VL/WH/WL
9
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ST92141 - GENERAL INFORMATION
9 GENERAL INFORMATION
9.1 PACKAGE MECHANICAL DATA 32-PIN SHRINK PLASTIC DUAL IN LINE PACKAGE
E See Lead Detail
Dim. A A1 A2
mm Min 0.51 3.05 3.56 0.36 0.46 0.76 1.02 0.20 0.25 Typ Max Min 0.020 3.56 3.76
inches Typ Max 5.08 0.140 0.148 0.200 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014
C
b
b1
b e3 D
eA eB
b1 C D E E1
27.43 27.94 28.45 1.080 1.100 1.120 9.91 10.41 11.05 0.390 0.410 0.435 7.62 8.89 1.78 10.16 12.70 2.54 3.05 Number of Pins 9.40 0.300 0.350 0.370 0.070 0.400 0.500 3.81 0.100 0.120 0.150 32
N E1 e 1 N/2
A2 A A1 L
e eA eB L
VR01725J
N
34-PIN PLASTIC SMALL OUTLINE PACKAGE
Dim. A A1 B 0.10mm .004 seating plane C D E e H h K L N SO34S
mm Min 2.46 0.13 0.36 0.23 17.73 7.42 1.02 10.16 0.64 0.61 10.41 0.400 0.74 0.025 0 1.02 0.024 Typ Max Min 2.64 0.097 0.29 0.005 0.48 0.014 0.32 0.0091 18.06 0.698 7.59 0.292
inches Typ Max 0.104 0.0115 0.019 0.0125 0.711 0.299 0.040 0.410 0.029 8 0.040
Number of Pins 34
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ST92141 - GENERAL INFORMATION
32-PIN SHRINK CERAMIC DUAL IN-LINE PACKAGE
Dim. A A1 B B1 C D D1 E E1 e G G1 G2 L O CDIP32SW N 0.38 0.36 0.46 0.64 0.89 0.20 0.25 26.67 10.16 1.78 9.40 14.73 1.12 3.30 7.37 32 mm Min Typ Max 3.63 0.015 0.58 0.014 0.018 0.023 1.14 0.025 0.035 0.045 0.36 0.008 0.010 0.014 1.050 0.400 0.070 0.370 0.580 0.044 0.130 0.290 Min inches Typ Max 0.143
29.41 29.97 30.53 1.158 1.180 1.202
9.45 9.91 10.36 0.372 0.390 0.408
Number of Pins
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ST92141 - GENERAL INFORMATION
9.2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 9.3 Transfer of Customer Code Customer code is made up of the FASTROM ( Factory Advanced Service Technique ROM) contents. The FASTROM contents are to be sent on diskette, or by electronic means, with the hexadecFigure 82. Sales Type Coding Rules imal file generated by the development tool. All unused bytes must be set to FFh. The customer code should be communicated to STMicroelectronics with the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Family Version Code Subfamily Number of pins ROM size Package Temperature Range FASTROM Code (three letters)
ST92 T 141 K 4 B 6 / xxx
0 = 25C B = Plastic DIP 4 = 16K 6 = Industrial D = Ceramic DIP 0 = Special (-40 to +85C) M = Plastic SOP
K= 32/34 pins P = FASTROM E = EPROM T = OTP
Table 31. Ordering Information
Sales Type 1) ST92P141K4B6/xxx ST92P141K4M6/xxx ST92E141K4D0 ST92T141K4B6 ST92T141K4M6 Program Memory (bytes) 16K FASTROM 16K EPROM 16K OTP RAM Package (bytes) 512 512 512 PSDIP32 SO34 CSDIP32W PSDIP32 SO34
Table 32. Development Tools
Development Tool Sales Type Real time emulator ST92141-EMU2 EPROM Programming Board ST92E141-EPB/EU ST92E141-EPB/US Remarks 220V Power Supply 110V Power Supply SDIP32 package
Gang Programmer
Third Party product available from Leap at www.leap.com.tw SO34 package ST9P-SWC/PC for PC
Note 1: xxx stands for the FASTROM code name assigned by STMicroelectronics.
C Hiware Compiler and Debugger
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ST92141 - GENERAL INFORMATION
STMicroelectronics OPTION LIST ST92P141 MICROCONTROLLER FAMILY (FASTROM DEVICE) ............................ ............................ ............................ Contact: ............................ Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference/FASTROM Code* :. . . . . . . . . . . . . . *The FASTROM code name is assigned by STMicroelectronics. STMicroelectronics reference: Device (PSDIP32): [ ] ST92P141K4B6/xxx* Customer: Address:
Device (SO34): Conditioning:
[ ] ST92P141K4M6/xxx* [ ] Tube [ ] Tape & Reel (not available for SDIP packages)
*xxx = FASTROM code name Software Development: [ ] STMicroelectronics [ ] Customer [ ] External laboratory
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" For marking, one line is possible with maximum 10 characters for PSDIP32 and 16 characters for SO34. Authorized characters are letters, digits, '.', '-', '/' and spaces only.
We have checked the FASTROM code verification file returned to us by STMicroelectronics. It conforms exactly with the FASTROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with device manufacture. Signature Date ............................ ............................
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ST92141 - SUMMARY OF CHANGES
10 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev. 1.7 Main Changes Added paragraph in section "PLL Clock Multiplier Programming" on page 66 about mandatory use of the divide-by-two prescaler for PLL operation. Updated Option List Date Oct 01
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ST92141 - SUMMARY OF CHANGES
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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